Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure
View Patent ↗A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the PFET using a same deposition and etching process. The method also includes providing stress materials in the source and drain regions of the NFET and the PFET.
1. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a first instruction generated for forming gate structures for an NFET and a PFET on a wafer;
a second instruction generated for forming sidewalls on the gate structures for the NFET and the PFET using a same deposition and etching process; and
a third instruction generated for providing stress materials in source and drain regions of the NFET and the PFET, wherein said third instruction further comprises:
forming, in a single masking process, recesses in source and drain regions of the NFET and the PFET in the wafer;
filling the recesses with a single type of stress material;
blocking one of the NFET and the PFET;
etching out the single type of stress material in the source and drain regions of an unblocked one of the NFET and the PFET to reform recesses; and
filling in the reformed recesses with a different type of stress material.
2. The design structure of claim 1 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
3. The design structure of claim 1 , wherein the single type of stress material is grown in the recesses and the different type of stress material is grown in the reformed recesses.
4. The design structure of claim 1 , wherein the recesses are formed by an etching process.
5. The design structure of claim 4 , wherein the third instruction further comprises additional etching of the recesses of one of the NFET and the PFET in order to make the recesses of one of the NFET and the PFET deeper than the recesses of the other of the NFET and the PFET.
6. The design structure of claim 5 , wherein:
the single type of stress material is eSiGe;
the different type of stress material is eSi:C; and
the etching out of the stress material is performed for the NFET.
7. The design structure of claim 5 , wherein
the single type of stress material is eSi:C;
the different type of stress material is eSiGe; and
the etching out of the stress material is performed for the PFET.
8. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a first instruction generated for forming gate structures for an NFET and a PFET on the wafer;
a second instruction generated for forming sidewalls on the gate structures for the NFET and the PFET using a same deposition and etching process;
a third instruction generated for forming recesses in source and drain regions of the NFET and the PFET in the wafer;
a fourth instruction generated for filling the recesses for the source and drain regions of the PFET with a first type of stress material;
a fifth instruction generated for filling the recesses of the NFET with the first type of stress material, prior to filling with a second type of stress material;
a sixth instruction generated for blocking the PFET;
a seventh instruction generated for etching out the first type of stress material in the source and drain regions of the NFET; and
an eight instruction generated for filling in the source and drain regions of the NFET with the second type of stress material.
9. The design structure of claim 8 , wherein the third generation further comprises forming, in a single masking process, the recesses in the source and drain regions of the NFET and the PFET.
10. The design structure of claim 8 , wherein the first type of stress material and the second type of stress material are grown in the recesses in separate processing steps.
11. The design structure of claim 10 , wherein the second type of stress material is deeper than the first type of stress material.
12. The design structure of claim 8 , wherein the first type of stress material and the second type of stress material are eSiGe and eSi:C, respectively.
13. The design structure of claim 8 , further comprises an additional instruction generated for providing additional etching of the recesses for the source and drain regions of one of the NFET and the PFET in order to make the recesses of one of the NFET and the PFET deeper than the recesses of the other of the NFET and the PFET.
14. The design structure of claim 8 , wherein the design structure comprises a netlist.
15. The design structure of claim 8 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
16. The design structure of claim 8 , wherein the design structure resides in a programmable gate array.