Body contacted hybrid surface semiconductor-on-insulator devices
View Patent ↗A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of a conductivity type opposite to the body region of the semiconductor fin. A metal semiconductor alloy portion is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region may be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects may be formed. A hybrid surface semiconductor-on-insulator (HSSOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) thus formed has a body region that is electrically tied to the source region.
1. A method of forming a semiconductor structure comprising:
forming a semiconductor fin having a first sidewall, a second sidewall, a first end wall, a second end wall, a substantially horizontal top surface, and a substantially horizontal bottom surface contacting a top surface of an insulator layer and having a doping of a first conductivity type, wherein said first and second sidewalls are substantially parallel to each other and substantially vertical, said first end wall is adjoined to one end of each of said first sidewall and said second sidewall, and said second end wall is adjoined to the other end of said first sidewall and said second sidewall and is substantially parallel to said first end wall;
forming a first source region having a doping of a second conductivity type directly beneath a portion of said first sidewall, directly beneath a portion of said first end wall, and within a first end portion of said semiconductor fin, wherein said second conductivity type is the opposite of said first conductivity type;
forming a second source region having a doping of said second conductivity type directly beneath a portion of said second sidewall, directly beneath another portion of said first end wall, and within said first end of said semiconductor fin, said second source region being laterally spaced from, and not contacting, said first source region;
forming a drain region directly beneath an entirety of said second end wall and within a second end of said semiconductor fin, said drain region having a doping of said second conductivity type, wherein said drain region does not contact said first and second source regions, and wherein said second end is located at an opposite side of said first end; and
forming a metal semiconductor alloy portion directly on said first source region, said second source region, and a top surface of a portion of said semiconductor fin having a doping of said first conductivity type and located between said first source region and said second source region.
2. The method of claim 1 , wherein said drain region is contiguous, wherein said end wall is substantially perpendicular to said first sidewall and said second sidewall.
3. The method of claim 1 , further comprising:
providing a semiconductor-on-insulator (SOI) layer including said insulator layer and a top semiconductor layer; and
forming a dielectric fin cap layer on said top semiconductor layer.
4. The method of claim 3 , further comprising patterning said dielectric fin cap layer and said top semiconductor layer, wherein a remaining portion of said dielectric fin cap layer constitutes a dielectric fin cap portion, wherein a remaining portion of said top semiconductor layer constitutes said semiconductor fin, and wherein said first sidewall and said second sidewall are substantially vertically coincident with sidewalls of said dielectric fin cap portion.
5. The method of claim 4 , wherein said dielectric fin cap portion overlies an entirety of said drain region, and wherein an edge of said dielectric fin cap portion is substantially aligned to said gate conductor.
6. The method of claim 4 , further comprising implanting dopants of said first conductivity type through a portion of said substantially horizontal top surface of said semiconductor fin located between said first source region and said second source region to form a first-conductivity-type doped region.
7. The method of claim 3 , further comprising:
forming a first gate dielectric directly on a middle portion of said first sidewall;
forming a second gate dielectric directly on a middle portion of said second sidewall; and
forming a gate conductor directly on said first gate dielectric, said second gate dielectric, and said dielectric fin cap portion.
8. The method of claim 1 , wherein said metal semiconductor alloy portion is formed as a structure that contiguously extends from a surface of said first source region to a surface of said second source region, and to said top surface of said portion of said semiconductor fin.
9. The method of claim 1 , further comprising forming a stack of a body region and a semiconductor region within said portion of said semiconductor fin having said doping of said first conductivity type, wherein an interface between said body region and said semiconductor region extends to said first end wall.
10. The method of claim 9 , wherein said body region vertically abuts said insulator layer and contacts said gate dielectric.
11. The method of claim 9 , wherein said semiconductor region is formed directly beneath a portion of said substantially horizontal top surface and directly beneath an upper portion of said first end wall and above, and directly on, a horizontal surface of said body region, wherein said semiconductor region is formed with a doping of said first conductivity type at a dopant concentration greater than a dopant concentration of said body region.
12. The method of claim 9 , wherein a first p-n junction is formed between said stack and said first source region.
13. The method of claim 12 , wherein said first source region is formed as a structure that vertically extends from said substantially horizontal top surface to a top surface of said insulator layer, and laterally extends from said first sidewall to said first end wall.
14. The method of claim 12 , wherein a second p-n junction is formed between said stack and said second source region, wherein said second source region is formed as a structure that vertically extends from said substantially horizontal top surface to a top surface of said insulator layer, and laterally extends from said second sidewall to said first end wall.
15. The method of claim 14 , wherein said first p-n junction and said second p-n junction are formed as structures that are not contiguous to each other and are laterally spaced from each other by said stack.
16. The method of claim 9 , wherein, after formation of said stack of said body region and said semiconductor region, each of said first vertical interface and said second vertical interface includes an interface between said body region and one of said first source region and said second source region and an interface between said semiconductor region and one of said first source region and said second source region.
17. The method of claim 1 , further comprising forming a gate dielectric directly on a portion of said first sidewall between said substantially horizontal top surface and said top surface of said insulator layer and directly on a portion of said second sidewall between said substantially horizontal top surface and said top surface of said insulator layer, wherein said gate dielectric does not contact said first end wall or said second end wall.
18. The method of claim 17 , wherein a first vertical interface between said first source region and a portion of said semiconductor fin having a doping of said first conductivity type is spaced from said first sidewall by a uniform width that is less than one half of a lateral distance between said first sidewall and said second sidewall.
19. The method of claim 18 , wherein a second vertical interface between said second source region and said portion of said semiconductor fin having said doping of said first conductivity type is spaced from said second sidewall.
20. The method of claim 19 , wherein said second vertical interface is spaced from said second sidewall by said uniform width.