Continuous metal semiconductor alloy via for interconnects
View Patent ↗A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion.
1. A semiconductor structure comprising:
at least one field effect transistor located on a surface of a semiconductor substrate, said at least one field effect transistor including at least a gate electrode, a source region and a drain region, and a spacer located on an exposed sidewall surface of the gate electrode;
a continuous metal semiconductor alloy comprising a single-crystal metal semiconductor alloy and including a lower portion that is contained within an upper surface of each of said source and drain regions, and a vertical pillar portion extending upwardly from said lower portion, wherein said lower portion and said vertical pillar portion are of unitary construction containing no material interface therebetween, and wherein said vertical pillar portion of the continuous metal semiconductor alloy maintains a same cross sectional along a vertical axis and does not contact an outer surface of said spacer, and wherein said vertical pillar portion has a lesser width than said lower portion;
a dielectric material having an upper surface that extends above an upper most surface of the at least one field effect transistor and is located on said surface of said semiconductor substrate, wherein said dielectric material embeds said vertical pillar portion of said continuous metal semiconductor alloy and wherein a top portion of said vertical pillar portion of said continuous metal semiconductor alloy directly contacts said upper surface of said dielectric material and is exposed; and
a metal line located on said top portion of said vertical pillar portion of the continuous metal semiconductor alloy and on said upper surface of said dielectric material.
2. The semiconductor structure of claim 1 wherein said single-crystal metal semiconductor alloy is a metal silicide.
3. The semiconductor structure of claim 1 wherein said single-crystal metal semiconductor alloy is a metal germanide.
4. The semiconductor structure of claim 1 wherein the continuous metal semiconductor alloy forms a conductive path between the source region and the metal line.
5. The semiconductor structure of claim 4 wherein said conductive path is ohmic.
6. The semiconductor structure of claim 4 wherein said conductive path exhibits variations in electrical potential that are linear.
7. The semiconductor structure of claim 1 wherein said semiconductor substrate comprises Si having a (100) crystal orientation.
8. The semiconductor structure of claim 1 further comprising a continuous single-crystal metal semiconductor alloy located atop said gate electrode.
9. The semiconductor structure of claim 1 wherein said continuous metal semiconductor alloy comprises a metal semiconductor alloy nanowire.