Carrier mobility enhanced channel devices and method of manufacture

1. A structure comprising:

an epitaxial grown germanium material formed directly and entirely on a substrate within a trench defined by sidewalls of a dummy gate structure; and

a dielectric material formed directly in contact with the germanium material,

wherein the germanium material is formed on the substrate below the sidewalls of the dummy gate structure.

2. The structure of claim 1 , wherein the dummy gate structure is filled with the dielectric material that lines inner portions of the sidewalls and a metal or metal alloy that contacts with the dielectric material.

3. The structure of claim 1 , wherein a gate oxide is formed on a dielectric layer formed over the dummy gate structure and the substrate, and outside of the trench.

4. The structure of claim 3 , further comprising a lightly doped P− region of a NFET device under the dummy gate structure.

5. The structure of claim 4 , further comprising:

N+ regions of the NFET device adjacent to the lightly doped P− region of the NFET device; and

metal contact regions in the N+ regions of the NFET device and completely below an uppermost surface of the substrate.

6. The structure of claim 3 , further comprising a lightly doped N− region of a PFET device under the dummy gate structure.

7. The structure of claim 6 , further comprising:

P+ regions of the PFET device adjacent to the lightly doped N− region of the PFET device; and

metal contact regions in the P+ regions of the PFET device and completely below an uppermost surface of the substrate.

8. A structure comprising:

a dummy gate structure on a substrate; and

a trench in the dummy gate structure which is partially filled with an epitaxial grown germanium material directly and entirely on the substrate, a gate oxide, and a gate conductor material,

wherein the gate oxide is on a dielectric layer and directly in contact with the germanium material, and the gate conductor is on the gate oxide over the dielectric layer, and

wherein the gate oxide and gate conductor are planarized to the dielectric layer such that the gate oxide and the gate conductor in the trench is coplanar with the upper surface of the dielectric layer,

wherein the germanium material is formed on the substrate below the sidewalls of the dummy gate structure.

9. The structure of claim 8 , wherein the germanium material is formed within the trench defined by sidewalls of the dummy gate structure.

10. The structure of claim 8 , wherein:

the trench is defined by sidewalls of the dummy gate structure; and

the trench is filled with the gate oxide which lines inner portions of the sidewalls, and the gate conductor which contacts the gate oxide.

11. The structure of claim 10 , wherein the dielectric layer is formed over the dummy gate structure and the substrate, and outside of the trench.

12. A design structure embodied in a machine readable memory for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

an epitaxial grown germanium material formed directly and entirely on a substrate and at least within a trench defined by sidewalls of a dummy gate structure, wherein the germanium material is formed below the sidewalls of the dummy gate structure;

a dielectric material that lines inner portions of the sidewalls, the dielectric material being formed directly in contact with the germanium material; and

a metal or metal alloy that contacts with the dielectric material.

13. The design structure of claim 12 , wherein the design structure comprises a netlist.

14. The design structure of claim 12 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

15. The design structure of claim 12 , wherein the design structure resides in a programmable gate array.

16. The method of claim 12 , wherein a gate oxide is formed on a dielectric layer formed over the dummy gate structure and the substrate, and outside of the trench.