Borderless interconnect line structure self-aligned to upper and lower level contact vias
View Patent ↗A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.
1. A method of forming a structure comprising:
forming an underlying metal via embedded in an underlying dielectric material layer on a substrate;
depositing a metal layer on a top surface of said underlying dielectric material layer;
patterning said metal layer to form a metal block having a facing pair of sidewalls; and
etching an upper portion of said underlying metal via within an area that does not underlie said metal block.
2. The method of claim 1 , further comprising forming an integrated line and via structure of integral construction by removing an upper portion of said metal block, wherein said integrated line and via structure includes a metal line having a substantially constant width and at least one overlying metal via having said substantially constant width.
3. The method of claim 2 , wherein said facing pair of sidewalls is spaced from each other by said substantially constant width.
4. The method of claim 2 , wherein a remaining portion of said upper portion of said underlying metal via after said etching forms an upper underlying metal via portion that has a pair of sidewalls laterally spaced by said substantially constant width.
5. The method of claim 2 , wherein said substrate includes a semiconductor substrate, and said method further comprises forming at least one semiconductor device on said semiconductor substrate, wherein said integrated line and via structure is electrically connected to said at least one semiconductor device.
6. The method of claim 2 , further comprising:
forming a dielectric material layer after said integrated line and via structure is formed; and
planarizing said dielectric material layer, wherein a top surface of said integrated line and via structure is coplanar with a top surface of said dielectric material layer.
7. The method of claim 6 , wherein a top surface of a lower underlying metal via portion of said underlying metal via is recessed during said etching of said upper portion of said underlying metal via.
8. The method of claim 7 , wherein a horizontal interface between said underlying dielectric material layer and said dielectric material layer is coplanar with said top surface of said lower underlying metal via portion.
9. The method of claim 6 , wherein a dielectric material having a dielectric constant less than 3.9 is deposited to form said dielectric material layer.