Self-aligned contacts for field effect transistor devices
View Patent ↗A field effect transistor device includes a gate stack disposed on a substrate a first contact portion disposed on a first distal end of the gate stack, a second contact portion disposed on a second distal end of the gate stack, the first contact portion disposed a distance (d) from the second contact portion, and a third contact portion having a width (w) disposed in a source region of the device, the distance (d) is greater than the width (w).
1. A field effect transistor device comprising:
a gate stack disposed on a substrate, the gate stack having a longitudinal axis parallel to a top surface of the substrate;
a first conductive contact portion disposed at a first distal end of a top surface of the gate stack;
a second conductive contact portion disposed at a second distal end of the top surface of the gate stack, the first conductive contact portion disposed a distance (d) from the second conductive contact portion, along the longitudinal axis; and
a third conductive contact portion having a width (w) disposed on a source region adjacent a first side of the gate stack, the width (w) of the third conductive contact portion defined along a direction parallel to the longitudinal axis, wherein the distance (d) is greater than the width (w) of the third conductive contact portion, such that the first and second conductive contacts are spaced and offset from opposite ends of the third conductive contact along the direction parallel to the longitudinal axis.
2. The device of claim 1 , wherein the first conductive contact portion and the second conductive contact portion contact a metal layer of the gate stack.
3. The device of claim 1 , wherein the source region includes a silicide material.
4. The device of claim 1 , wherein the gate stack includes a dielectric layer disposed on the substrate, a metal layer disposed on the dielectric layer, a silicon layer disposed on the metal layer, and a hardmask layer disposed on the silicon layer.
5. The device of claim 1 , wherein the source region and the drain region are arranged on a silicon region of the substrate.
6. The device of claim 1 , wherein the substrate includes a silicon region and a silicon-on-insulator trench region (SOI).
7. The device of claim 1 , further including a spacer arranged adjacent to the gate stack, wherein the spacer includes a first nitride layer and a second nitride layer.
8. The device of claim 1 , further including a spacer arranged adjacent to the gate stack, wherein the spacer includes first nitride material.
9. A field effect transistor device comprising:
a gate stack disposed on a substrate, the gate stack having a longitudinal axis parallel to a top surface of the substrate;
a first conductive contact portion disposed at a first distal end of a top surface of the gate stack;
a second conductive contact portion disposed at a second distal end of the top surface of the gate stack, the first conductive contact portion disposed a distance (d) from the second conductive contact portion, along the longitudinal axis;
a third conductive contact portion having a width (w) disposed on a source region adjacent a first side of the gate stack, the width (w) of the third conductive contact portion defined along a direction parallel to the longitudinal axis, wherein the distance (d) is greater than the width (w) of the third conductive contact portion, such that the first and second conductive contacts are spaced and offset from opposite ends of the third conductive contact along the direction parallel to the longitudinal axis; and
a fourth conductive contact portion having a width (w) disposed on a drain region adjacent a second side of the gate stack, the width (w) of the fourth conductive contact portion defined along a direction parallel to the longitudinal axis, wherein the distance (d) is greater than the width (w) of the fourth conductive contact portion, such that the first and second conductive contacts are spaced and offset from opposite ends of the fourth conductive contact along the direction parallel to the longitudinal axis.
10. The device of claim 9 , wherein the first conductive contact portion and the second conductive contact portion contact a metal layer of the gate stack.
11. The device of claim 9 , wherein the source region and the drain region include a silicide material.
12. The device of claim 9 , wherein the gate stack includes a dielectric layer disposed on the substrate, a metal layer disposed on the dielectric layer, a silicon layer disposed on the metal layer, and a hardmask layer disposed on the silicon layer.
13. The device of claim 9 , wherein the source region and the drain region are arranged on a silicon region of the substrate.
14. The device of claim 9 , wherein the substrate includes a silicon region and a silicon-on-insulator trench region (SOI).
15. The device of claim 9 , further including a spacer arranged adjacent to the gate stack, wherein the spacer includes a first nitride layer and a second nitride layer.
16. The device of claim 9 , further including a spacer arranged adjacent to the gate stack, wherein the spacer includes first nitride material.