IP Library Granted Patent US 8,859,389
Granted Patent B2
US 8,859,389 · App. 13/015,857 · Granted Oct 14, 2014

Methods of making fins and fin field effect transistors (FinFETs)

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Quick Facts
Patent No.
US 8,859,389
App. No.
13/015,857
Granted
Oct 14, 2014
Kind
B2
Abstract

Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over a semiconductor substrate. The multi-layer structure comprises a first layer over the semiconductor substrate, a second layer over the first layer, and a third layer over the second layer. The method also comprises removing upper portions of the semiconductor substrate and portions of the multi-layer structure to form fins of the semiconductor substrate and portions of the multi-layer structure. Further, the method comprises selectively oxidizing the first layer while oxidization of the second layer and the third layer is less than the oxidization of the first layer. The oxidation can be performed before gap fill recess or after gap fill recess.

Claims (25)

1. A method of forming fins, comprising:

forming a multi-layer structure over a semiconductor substrate, the multi-layer structure comprises a silicon-germanium layer as a first layer over the semiconductor substrate, a silicon layer as a second layer over the first layer, and a third layer over the second layer wherein the silicon layer is electrically in contact with the semiconductor substrate via the silicon-germanium layer;

removing upper portions of the semiconductor substrate and portions of the multi-layer structure to form fins of the semiconductor substrate and portions of the multi-layer structure; selectively oxidizing the silicon-germanium layer while oxidization of the second layer is less than the oxidization of the first layer, wherein the silicon-germanium layer is turned into a SiGeOxide layer and wherein the silicon layer is electrically separated from the semiconductor substrate by the SiGeOxide layer;

filling gaps between the fins with an insulating material after the selectively oxidizing; and

recessing at least a portion of the insulating material to expose a fin, wherein at least a side surface of the second layer or a top surface of the fin is exposed, and at least a part of side surfaces of the SiGeOxide layer is uncovered from the recessed insulating material.

2. The method of claim 1 , the selectively oxidizing comprises stopping the oxidization before the first layer is fully oxidized.

3. The method of claim 1 , the selectively oxidizing is conducted for up to about 30 minutes.

4. The method of claim 1 , the selectively oxidizing is performed at a temperature range between about 500 and 800 degrees Celsius.

5. The method of claim 1 , the selectively oxidizing is performed in an atmosphere containing chlorine.

6. The method of claim 1 , the semiconductor substrate is a bulk-Si substrate.

7. The method of claim 1 , further comprising controlling a thickness of the second layer and the third layer.

8. The method of claim 1 , the filling provides insulation of a Si-fin channel and supporting substrate.

9. The method of claim 1 , the insulating material is silicon dioxide.

10. The method of claim 1 , the second layer and the third layer are epitaxially grown.

11. A method of forming a shallow trench isolation recess, comprising:

growing a multi-layer structure comprising three or more layers over a semiconductor substrate wherein the three layers are a silicon-germanium layer as a first layer over the semiconductor substrate, a silicon layer as a second layer over the first layer, and a third layer over the second layer and wherein the silicon layer is electrically in contact with the semiconductor substrate via the silicon-germanium layer;

removing upper portions of the semiconductor substrate and portions of the multi-layer structure, thereby forming fins;

forming isolation material between the fins;

selectively oxidizing at least a portion of the fins, comprising:

selectively oxidizing the silicon-germanium layer while oxidization of the second layer is less than the oxidization of the first layer, wherein the silicon-germanium layer is turned into a SiGeOxide layer, and wherein the silicon layer is electrically separated from the semiconductor substrate by the SiGeOxide layer; and

performing an etching process to remove at least a layer of isolation material to expose an underlying layer, wherein at least a part of side surfaces of the SiGeOxide layer and at least a side surface of the second layer are exposed from the isolation material.

12. The method of claim 11 , the selectively oxidizing comprises stopping the oxidization before a first layer of the multi-layer structure is fully oxidized.

13. The method of claim 11 , the forming comprises forming silicon dioxide between the fins.

14. The method of claim 1 , a part of the silicon layer is oxidized during the selectively oxidizing the silicon-germanium layer.

15. The method of claim 11 , a part of the silicon layer is oxidized during selectively oxidizing the at least the portion of the fins.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2017
From: GLOBALFOUNDRIES INC.
To: AURIGA INNOVATIONS, INC.
Reel/Frame 041804/0940 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2015
From: VEERARAGHAVAN, BASKER
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 034672/0824 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEES (GLOBALFOUNDRIES INC. & INTERNATIONAL BUSINESS MACHINES CORPORATION) THAT WERE ERRONEOUSLY AND PREVIOUSLY RECORDED ON REEL 025712 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT ASSIGNEE IS TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. Recorded Jan 9, 2015
From: KAWASAKI, HIROHISA
To: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
Reel/Frame 034747/0699 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2015
From: ADHIKARI, HEMANT; MASZARA, WITOLD
To: GLOBALFOUNDRIES INC.
Reel/Frame 034672/0813 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2012
From: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 027700/0242 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2011
From: KAWASAKI, HIROHISA; VEERARAGHAVAN, BASKER; ADHIKARI, HEMANT; MASZARA, WITOLD
To: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.; GLOBALFOUNDRIES INC.; INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 025712/0827 →