Formation of multi-height MUGFET
View Patent ↗A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure and a second rectangular fin structure, both positioned on a substrate. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. A gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure. The gate conductor is positioned adjacent to a relatively larger portion of the sides of the second rectangular fin structure and is positioned adjacent to a relatively smaller portion of the sides of the first rectangular fin structure.
1. A method comprising:
forming trench isolation regions in a silicon layer of a substrate to define a first silicon region and a second silicon region bounded by said trench isolation regions;
patterning a first hardmask layer to form a first hardmask island on said first silicon region and a second hardmask island on said second silicon region;
patterning a second hardmask layer on said first silicon region and said first hardmask island and on said second silicon region and said second hardmask island;
removing said second hardmask layer from said second silicon region and said second hardmask island to provide second exposed areas of said second silicon region;
patterning first and second mandrels over said first silicon region and said second silicon region;
forming a third hardmask layer over said substrate;
removing said first and second mandrels to form openings in said third hardmask layer;
etching said second exposed areas of said second silicon region to form second trenches to a second depth in said second silicon region;
removing said second hardmask layer from said first silicon region and said first hardmask island to provide first exposed areas of said first silicon region; and
simultaneously etching said first exposed areas of said first silicon region to form first trenches to a first depth in said first silicon region and further etching said second trenches to a third depth, said third depth being greater than said first depth.
2. The method according to claim 1 , said simultaneously etching exposing a greater sidewall area of said second silicon region relative to said first silicon region.
3. The method according to claim 1 , said substrate comprising a silicon-on-insulator substrate comprising said silicon layer on a buried oxide layer, said etching of said second trenches to said third depth exposes said buried oxide layer.
4. The method according to claim 1 , said first silicon region and said second silicon region being one of:
adjacent one another and forming parts of a single transistor device; and
separated from one another on said substrate, and forming parts of different transistor devices on said substrate.
5. The method according to claim 1 , said first silicon region and said second silicon region forming one of a multiple gate field effect transistor (MUGFET) and a fin-type field effect transistor (FINFET).
6. A method comprising:
forming trench isolation regions in a silicon layer of a substrate to define a first silicon region and a second silicon region bounded by said trench isolation regions;
patterning a first hardmask layer to form a first hardmask island on said first silicon region and a second hardmask island on said second silicon region;
patterning a second hardmask layer on said first silicon region and said first hardmask island and on said second silicon region and said second hardmask island;
removing said second hardmask layer from said second silicon region and said second hardmask island to provide second exposed areas of said second silicon region;
patterning first and second mandrels over said first silicon region and said second silicon region;
forming a third hardmask layer over said substrate;
removing said first and second mandrels to form openings in said third hardmask layer;
etching said second exposed areas of said second silicon region to form second trenches to a second depth in said second silicon region;
removing said second hardmask layer from said first silicon region and said first hardmask island to provide first exposed areas of said first silicon region;
simultaneously etching said first exposed areas of said first silicon region to form first trenches to a first depth in said first silicon region and further etching said second trenches to a third depth, said third depth being greater than said first depth;
removing said third hardmask layer to leave said first silicon region and said second silicon region exposed as silicon fins;
patterning a source and drain protective layer over said silicon fins, said source and drain protective layer protecting source and drain regions of said silicon fins and leaving channel regions of said silicon fins exposed;
forming a gate insulator on said channel regions;
patterning at least one gate conductor on said gate insulator;
removing said source and drain protective layer; and
implanting an impurity into said source and drain regions.
7. The method according to claim 6 , said simultaneously etching exposing a greater sidewall area of said second silicon region relative to said first silicon region.
8. The method according to claim 6 , said substrate comprising a silicon-on-insulator substrate comprising said silicon layer on a buried oxide layer, said etching of said second trenches to said third depth exposes said buried oxide layer.
9. The method according to claim 6 , said first silicon region and said second silicon region being one of:
adjacent one another and forming parts of a single transistor device; and
separated from one another on said substrate, and forming parts of different transistor devices on said substrate.
10. The method according to claim 6 , said first silicon region and said second silicon region forming one of a multiple gate field effect transistor (MUGFET) and a fin-type field effect transistor (FINFET).