Semiconductor device having a copper plug
Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.
1. A semiconductor device comprising:
a semiconductor substrate having a plurality of wiring layers wherein a last wiring layer comprises a conductive material;
an insulation layer formed on the last wiring layer, the insulation layer having a via opening formed therein to expose the conductive material in the last wiring layer;
a barrier layer formed in the via opening;
a copper plug formed on the barrier layer and filling the via opening wherein the copper plug has a wall which makes an angle with respect to the last wiring layer of 45 to 75 degrees;
a cap layer formed on the insulation layer and directly covering the copper plug to prevent oxidation of the copper in the copper plug, the cap layer making direct contact with the wall; and
a dielectric layer formed directly on the cap layer and having an opening aligned with the copper plug, the dielectric layer opening being larger than the copper plug such that the dielectric opening exposes the cap layer covering the copper plug and in addition exposes a portion of the cap layer that is not covering the copper plug.
2. The semiconductor device of claim 1 wherein the cap layer is a nitride layer.
3. The semiconductor device of claim 1 wherein the copper plug is a terminal pad.
4. A semiconductor device comprising:
a semiconductor substrate having a last wiring layer that comprises a conductive material;
an insulation layer formed on the last wiring layer, the insulation layer having a via opening formed therein to expose the conductive material in the last wiring layer;
a copper plug formed in, and filling, the via opening wherein the copper plug has a wall which makes an angle with respect to the last wiring layer of 45 to 75 degrees;
a cap layer formed on the insulation layer and directly covering the copper plug to prevent oxidation of the copper in the copper plug, the cap layer making direct contact with the wall; and
a dielectric layer formed directly on the cap layer and having an opening aligned with the copper plug and with the cap layer covering the copper plug, the dielectric layer opening being larger than the copper plug such that the dielectric opening exposes the cap layer covering the copper plug and in addition exposes a portion of the cap layer that is not covering the copper plug.
5. The semiconductor device of claim 4 wherein the copper plug is a terminal pad.
6. A semiconductor device comprising:
a semiconductor substrate having a plurality of wiring layers wherein a last wiring layer comprises a conductive material;
an insulation layer formed on the last wiring layer, the insulation layer having a via opening formed therein to expose the conductive material in the last wiring layer;
a barrier layer formed in the via opening;
a copper plug formed on the barrier layer and filling the via opening;
a cap layer formed on the insulation layer and covering the copper plug to prevent oxidation of the copper in the copper plug;
a dielectric layer formed directly on the cap layer and having an opening aligned with the copper plug; and
ball limiting metallurgy formed on the dielectric layer and in the opening.
7. A semiconductor device comprising:
a semiconductor substrate having a last wiring layer that comprises a conductive material;
an insulation layer formed on the last wiring layer, the insulation layer having a via opening formed therein to expose the conductive material in the last wiring layer;
a copper plug formed in, and filling, the via opening;
a cap layer formed on the insulation layer and covering the copper plug to prevent oxidation of the copper in the copper plug; and
a dielectric layer formed directly on the cap layer and having an opening aligned with the copper plug and with the cap layer covering the copper plug; and
ball limiting metallurgy formed on the dielectric layer and in the opening.