Borderless interconnect line structure self-aligned to upper and lower level contact vias
View Patent ↗A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.
1. A structure comprising:
an integrated line and via structure of integral construction embedded in an upper portion of a dielectric material layer, said integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having said substantially constant width, and sidewalls of said at least one overlying metal via are vertically coincident with sidewalls of said metal line; and
an underlying metal via including an upper underlying metal via portion and a lower underlying metal via portion, wherein said upper underlying metal via portion has a pair of sidewalls laterally spaced by said substantially constant width and is embedded in a lower portion of said dielectric material layer.
2. The structure of claim 1 , wherein said underlying metal via has a horizontal surface that is a top surface of said lower underlying metal via portion and adjoins a bottom edge of one of said pair of sidewalls.
3. The structure of claim 2 , wherein said underlying metal via has another pair of sidewalls, wherein said other pair of sidewalls extends throughout said upper underlying metal via portion and said lower underlying metal via portion, is separated by a second substantially constant width, and adjoins substantially vertical edges of said pair of sidewalls of said upper underlying metal via portion.
4. The structure of claim 2 , wherein said lower underlying metal via portion is embedded in an underlying dielectric material layer.
5. The structure of claim 4 , wherein a horizontal interface between said underlying dielectric material layer and said dielectric material layer is coplanar with said top surface of said lower underlying metal via portion.
6. The structure of claim 1 , wherein a top surface of said integrated line and via structure is coplanar with a top surface of said dielectric material layer.
7. The structure of claim 1 , wherein an entirety of said integrated line and via structure is composed of a same conductive material.
8. The structure of claim 1 , wherein an entirety of said integrated line and via structure and said upper underlying metal via portion are located within a pair of substantially vertical planes including said sidewalls of said metal line.
9. The structure of claim 1 , wherein said upper portion of said dielectric material layer and said lower portion of said dielectric material layer are of integral construction without an interface therebetween.
10. The structure of claim 9 , wherein said dielectric material layer includes a dielectric material having a dielectric constant less than 3.9.
11. The structure of claim 1 , further comprising a semiconductor substrate including at least one semiconductor device and located under said underlying dielectric material layer, wherein said at least one semiconductor device is electrically connected to said integrated line and via structure.