Flip-flop circuit and prescaler circuit including the same

1. A prescaler circuit that divides a frequency of a clock signal by an integer 3 or 4 comprising:

a first flip-flop circuit that detects second output data in synchronization with the clock signal and outputs the detected data as first output data; and

a second flip-flop circuit that detects the first output data in synchronization with the clock signal and outputs the detected data as the second output data to the first flip-flop circuit;

wherein the first flip-flop circuit comprises:

a master-side latch circuit that generates intermediate data in synchronization with the clock signal;

a slave-side latch circuit that detects the intermediate data in synchronization with the clock signal and outputs the detected intermediate data as the first output data; and

the control signal switching circuit that selects and outputs the first output data as a control signal in a mode where the frequency is divided by 3, and selects and outputs a predefined fixed signal as a control signal in a mode where the frequency is divided by 4; and

wherein the master-side latch circuit generates the intermediate data based on the second output data and the control signal.

2. The prescaler circuit according to claim 1 , wherein the master-side latch circuit comprises:

a first differential circuit provided between a first power supply terminal and a second power supply terminal, an on-off state of the first differential circuit being controlled based on the second output data;

a second differential circuit provided between the first differential circuit and the first power supply terminal, an on-off state of the second differential circuit being controlled based on the control signal; and

a third differential circuit provided between the first differential circuit and the first power supply terminal, the third differential circuit being configured to hold and output a drain voltage of the first differential circuit as the intermediate data.

3. The prescaler circuit according to claim 2 , wherein the second differential circuit comprises:

a first transistor provided between a common source of the first differential circuit and the first power supply terminal; and

a second transistor provided between a drain of the first differential circuit and the first power supply terminal.

4. The prescaler circuit according to claim 3 , wherein

the control signal switching circuit controls an on-off state of the second transistor in accordance with a selected signal between one of a pair of signals constituting the first output data and a first power supply voltage from the first power supply terminal, the selected signal being selected based on the control signal, and

the control signal switching circuit also controls an on-off state of the first transistor in accordance with a selected signal between the other one of the pair of signals constituting the first output data and a second power supply voltage from the second power supply terminal, the second power supply voltage being different from the first power supply voltage, and the selected signal being selected based on the control signal.

5. The prescaler circuit according to claim 2 , further comprising a bias voltage control transistor provided between the second differential circuit and the first power supply terminal.

6. The prescaler circuit according to claim 2 , wherein the first differential circuit is formed from a pair of N-channel MOS transistors.

7. The prescaler circuit according to claim 2 , wherein the second differential circuit is formed from a pair of N-channel MOS transistors.

8. The prescaler circuit according to claim 2 , wherein the third differential circuit is formed from a pair of NPN-type bipolar transistors.

9. A flip-flop circuit comprising:

a master-side latch circuit that generates intermediate data in synchronization with a clock signal;

a slave-side latch circuit that detects the intermediate data in synchronization with the clock signal and outputs the detected intermediate data as a first output data; and

a control signal switching circuit that selects and outputs the first output data as a control signal in a mode where the frequency is divided by 3, and selects and outputs a predefined fixed signal as the control signal in a mode where the frequency is divided by 4; and

wherein the master-side latch circuit generates the intermediate data based on externally-supplied input data and the control signal.

10. The prescaler circuit according to claim 9 , wherein the master-side latch circuit comprises:

a first differential circuit provided between a first power supply terminal and a second power supply terminal, an on-off state of the first differential circuit being controlled based on the externally-supplied input data;

a second differential circuit provided between the first differential circuit and the first power supply terminal, an on-off state of the second differential circuit being controlled based on the control signal; and

a third differential circuit provided between the first differential circuit and the first power supply terminal, the third differential circuit being configured to hold and output a drain voltage of the first differential circuit as the intermediate data.