LAYOUT DESIGN METHOD, LAYOUT DESIGN PROGRAM, AND LAYOUT DESIGN APPARATUS
It is desired to make it possible to generate a layout whose chip area is small for a semiconductor integrated circuit having a plurality of power supply systems in an internal circuit region. Power supply line of a first power supply is generated in an internal circuit region. Each of primitive cells is generated so that it is connected to the power supply line. It is checked whether or not the timing of a signal supplied to each of the primitive cells from the power supply line of the first power supply satisfies a prescribed criterion. A line for supplying a second potential generated by a second power supply to replace a first potential generated by the first power supply is generated for at least one power supply separation object cell being at least one of the primitive cells after it is checked that the prescribed criterion is satisfied.
1 . A layout design method comprising:
generating a power supply line of a first power supply in a layout of an internal circuit region;
generating an arrangement of each of a plurality of primitive cells to connect to the power supply line;
checking whether or not a timing of a signal supplied to each of the plurality of primitive cells from the power supply line of the first power supply satisfies a prescribed criterion; and
generating a line for supplying a second potential generated by a second power supply to replace a first potential generated by the first power supply for at least one power supply separation object cell being at least one of the plurality of primitive cells after it is checked that the prescribed criterion is satisfied.
2 . The layout design method according to claim 1 , wherein the generating the line for supplying the second potential comprises:
identifying a potential which is supplied to each of the at least one power supply separation object cell;
identifying a power supply separation power supply line configured to supply the second potential to each of the at least one power supply separation object cell among the power supply line of the first power supply which is generated at the generating the power supply line of the first power supply;
dividing the power supply separation power supply line between the first power supply and each of the at least one power supply separation object cell;
deleting a through hole configured to supply a potential different from the second potential to each of the at least one power supply separation object cell after the dividing; and
connection the second power supply to the power supply separation power supply line.
3 . A computer program product embodied on a computer-readable medium and comprising code that, when executed, causes a computer to perform the following:
generating a power supply line of a first power supply in a layout of an internal circuit region;
generating an arrangement of each of a plurality of primitive cells to connect to the power supply line;
checking whether or not a timing of a signal supplied to each of the plurality of primitive cells from the power supply line of the first power supply satisfies a prescribed criterion; and
generating a line for supplying a second potential generated by a second power supply to replace a first potential generated by the first power supply for at least one power supply separation object cell being at least one of the plurality of primitive cells after it is checked that the prescribed criterion is satisfied.
4 . A computer program product according to claim 3 further comprising code that, when executed, causes the computer to perform the following:
identifying a potential which is supplied to each of the at least one power supply separation object cell;
identifying a power supply separation power supply line configured to supply the second potential to each of the at least one power supply separation object cell among the power supply line of the first power supply which is generated at the generating the power supply line of the first power supply;
dividing the power supply separation power supply line between the first power supply and each of the at least one power supply separation object cell;
deleting a through hole configured to supply a potential different from the second potential to each of the at least one power supply separation object cell after the dividing; and
connection the second power supply to the power supply separation power supply line.
5 . A layout design apparatus comprising:
a single power supply wiring section configured to generate a power supply line of a first power supply in a layout of an internal circuit region;
a primitive cell generation section configured to generate an arrangement of each of a plurality of primitive cells to connect to the power supply line;
a timing check section configured to check whether or not a timing of a signal supplied to each of the plurality of primitive cells from the power supply line of the first power supply satisfies a prescribed criterion; and
a potential changeover section configured to generate generating a line for supplying a second potential generated by a second power supply to replace a first potential generated by the first power supply for at least one power supply separation object cell being at least one of the plurality of primitive cells after it is checked that the prescribed criterion is satisfied.
6 . The layout design apparatus according to claim 5 , wherein the potential changeover section comprises:
a potential identification section configured to identify a potential which is supplied to each of the at least one power supply separation object cell;
a power supply separation power supply line identification section configured to identify a power supply separation power supply line configured to supply the second potential to each of the at least one power supply separation object cell among the power supply line of the first power supply which is generated at the generating the power supply line of the first power supply;
a division section configured to divide the power supply separation power supply line between the first power supply and each of the at least one power supply separation object cell;
deletion section configured to delete a through hole configured to supply a potential different from the second potential to each of the at least one power supply separation object cell after the dividing; and
a connection section configured to connect the second power supply to the power supply separation power supply line.