Programmable impedance element circuits and methods

1. An integrated circuit, comprising:

a plurality of sub bit line groups, each sub bit line group coupled to a different main bit line by a corresponding access device; and

a plurality of programmable impedance elements comprising programmable metallization cells (PMCs) arranged into element groups, each element group being coupled to a corresponding sub bit line, and each programmable impedance element of a same element group having a first terminal coupled to the corresponding sub bit line, and a second terminal coupled to a different anode line.

2. The integrated circuit of claim 1 , wherein:

the sub bit lines are disposed in a first direction, substantially parallel to one another; and

the anode lines are disposed in a second direction, substantially parallel to one another.

3. The integrated circuit of claim 1 , wherein:

the sub bit lines are formed adjacent to one another in an area having first ends disposed adjacent to one side of the area and second ends disposed adjacent to a second side of the area,

one set of the sub bit lines being coupled to their corresponding access device at their first ends, and

another set of the sub bit lines being coupled to their corresponding access device at their second ends.

4. The integrated circuit of claim 1 , wherein:

at least one of the programmable impedance elements of an element group has a different structure than the other programmable impedance elements of the same element group.

5. The integrated circuit of claim 1 , wherein

at least one of the programmable impedance elements of an element group has a different data retention time than the other programmable impedance elements of the same element group.

6. The integrated circuit of claim 1 , further including:

the programmable impedance elements are arranged into an array of rows and columns, each programmable impedance element being formed at an intersection of sub bit lines disposed in the column direction and anode lines disposed in the row direction.

7. The integrated circuit of claim 1 , wherein:

the PMCs have cathodes formed from at least a portion of the sub bit lines, and anodes formed from at least a portion of the anode lines.

8. The integrated circuit of claim 1 , further including:

a plurality of anode lines disposed substantially perpendicular to the sub bit lines, each anode line coupled to at least one programmable impedance element;

a regular decoder that activates at least one regular anode line in response to address data; and

a redundancy circuit that activates one redundant anode line, and disables a number of other anode lines in response to the address data matching a predetermined value.

9. The integrated circuit of claim 1 , further including:

the sub bit lines being formed from a first metallization layer and being substantially parallel to one another with adjacent sub bit line pairs being formed within a pitch of the access devices;

a plurality of anode lines substantially perpendicular to, and over, the sub bit lines; and

the main bit line is formed from a second metallization layer over the anode lines; wherein

the programmable impedance elements are formed at intersections of the sub bit lines and anode lines.