Multi-level triggering circuit

1. Circuitry comprising:

a comparator to compare an input analog signal to a threshold and to output a signal that is based on comparison of the input analog signal to the threshold;

a first circuit path to receive the signal and to detect a characteristic of the signal, the first circuit path being configured to support triggering at a first frequency;

a second circuit path to receive the signal and to detect the characteristic of the signal, the second circuit path being configured to support triggering at a second frequency, the second frequency being lower than the first frequency; and

a selector to select an output of the first circuit path or an output of the second circuit path.

2. The circuitry of claim 1 , wherein the first circuit path is a part of an integrated circuit and the second circuit path is part of a field-programmable gate array (FPGA).

3. The circuitry of claim 2 , wherein the integrated circuit and the FPGA are parts of a digital storage oscilloscope (DSO); and

wherein the FPGA is configured to include functionality for the DSO that is separate from, and in addition to, the second circuit path.

4. The circuitry of claim 2 , wherein the integrated circuit consumes more power than the FPGA to perform triggering.

5. The circuitry of claim 2 , wherein the FPGA further comprises advanced triggering logic to perform processing on the signal.

6. The circuitry of claim 1 , wherein the first circuit path comprises an edge detector for detecting either a rising edge or a falling edge of the signal;

wherein the second circuit path comprises an edge detector for detecting either the rising edge or the falling edge of the signal; and

wherein the characteristic detected by the first circuit path and the second circuit path comprises the rising edge or the falling edge.

7. The circuitry of claim 1 , wherein the first frequency is about 1 GHz or less and the second frequency is about 600 MHz or less.

8. The circuitry of claim 1 , wherein the first circuit path comprises a first flip-flop triggered by a first version of the signal and a second flip-flop, in series with the first flip-flop and triggered by a time-delayed version of the signal.

9. The circuitry of claim 1 , wherein the second circuit path comprises:

triggering logic to generate an intermediate signal based on a version of the signal; and

a first flip-flop triggered by the intermediate signal and a second flip-flop that is in series with the first flip-flop and triggered by a time-delayed version of the intermediate signal.

10. The circuitry of claim 8 , wherein the second circuit path comprises:

triggering logic to generate an intermediate signal based on a version of the signal; and

a first flip-flop triggered by the intermediate signal and a second flip-flop that is in series with the first flip-flop and triggered by a time-delayed version of the intermediate signal.

11. A digital storage oscillator (DSO) comprising:

an analog to digital converter (ADC) to convert an input analog signal into a digital signal in accordance with a clock signal;

circuitry to generate a trigger signal, the circuitry comprising:

a comparator to identify a trigger event for the input analog signal;

an edge selector to identify a rising or falling edge of a signal output by the comparator and to produce an asynchronous trigger signal; and

a latch to output the trigger signal based on the asynchronous trigger signal and a version of a clock signal; and

a time interval digitizer to determine a time difference that is based on the asynchronous trigger signal, the time difference being a difference between an actual time that the trigger event occurred and a time that a clock signal running the ADC occurred;

wherein the edge selector comprises:

a first circuit path to receive the signal and to detect a characteristic of the signal, the first circuit path being configured to support triggering at a first frequency;

a second circuit path to receive the signal and to detect the characteristic of the signal, the second circuit path being configured to support triggering at a second frequency, the second frequency being lower than the first frequency; and

a selector to select an output of the first circuit path or an output of the second circuit path to provide to the time interval digitizer.

12. The DSO of claim 11 , further comprising:

memory; and

a controller to capture data from the ADC based on the time difference, and to store the data in the memory.

13. The DSO of claim 11 , wherein the first circuit path is a part of an integrated circuit and the second circuit path is part of a field-programmable gate array (FPGA).

14. The DSO of claim 13 , wherein the FPGA is configured to include functionality for the DSO that is separate from, and in addition to, the second circuit path.

15. The DSO of claim 13 , wherein the integrated circuit consumes more power than the FPGA to perform triggering.

16. The DSO of claim 13 , wherein the FPGA further comprises advanced triggering logic to perform processing on the signal.

17. The DSO of claim 11 , wherein the characteristic detected by the first circuit path and the second circuit path comprises the rising edge or the falling edge.

18. The DSO of claim 11 , wherein the first frequency is about 1 GHz or less and the second frequency is about 600 MHz or less.

19. The DSO of claim 11 , wherein the first circuit path comprises a first flip-flop triggered by a first version of the signal and a second flip-flop that is in series with the first flip-flop and triggered by a time-delayed version of the signal.

20. The DSO of claim 11 , wherein the second circuit path comprises:

triggering logic to generate an intermediate signal based on a version of the signal; and

a first flip-flop triggered by the intermediate signal and a second flip-flop that is in series with the first flip-flop and triggered by a time-delayed version of the intermediate signal.

21. The DSO of claim 19 , wherein the second circuit path comprises:

triggering logic to generate an intermediate signal based on a version of the signal; and

a first flip-flop triggered by the intermediate signal and a second flip-flop that is in series with the first flip-flop and triggered by a time-delayed version of the intermediate signal.