Driving an electronic instrument

1. Circuitry comprising:

a pre-amplifier having a differential output, wherein the differential output corresponds to a common mode voltage;

a multiplexer comprised of sets of transistors, each transistor having a control input;

a comparator comprising input terminals, a first terminal of the input terminals to receive a signal that is based on an output of the multiplexer, and a second terminal of the input terminals to receive a threshold voltage;

a compensation circuit to produce a divided voltage that varies in accordance with variations in the common mode voltage; and

an amplifier to receive a predefined voltage and to use the divided voltage to affect the predefined voltage to produce the threshold voltage for the comparator;

wherein signals in the differential output of the pre-amplifier are applicable to corresponding control inputs in the sets of transistors.

2. The circuitry of claim 1 , wherein the control input of each transistor comprises a base, each transistor also comprising an emitter and a collector; and

wherein transistors in the sets of transistors are electrically connected collector-to-collector and emitter-to-emitter.

3. The circuitry of claim 2 , wherein the sets of transistor comprises two pairs of transistors, each pair of transistors being electrically connected collector-to-collector and emitter-to-emitter.

4. The circuitry of claim 1 , wherein the comparator is configured to output a signal in response to the signal received by the comparator exceeding the threshold voltage.

5. The circuitry of claim 1 , wherein the amplifier is configured to incorporate the divided voltage into the predefined voltage to produce the threshold voltage.

6. The circuitry of claim 1 , wherein the pre-amplifier is a first pre-amplifier, the common mode voltage is a first common mode voltage, the comparator is a first comparator, the amplifier is a first amplifier; and

wherein the circuitry further comprises:

a second pre-amplifier having a differential output, wherein the differential output of the second pre-amplifier corresponds to a second common mode voltage;

a second comparator comprising second input terminals, a first terminal of the second input terminals to receive a second signal that is based on a second output of the multiplexer, and a second terminal of the second input terminals to receive a second threshold voltage;

wherein the compensation circuit is configured to produce a second divided voltage that varies in accordance with variations in the second common mode voltage; and

a second amplifier to receive a second predefined voltage and to use the second divided voltage to affect the second predefined voltage to produce the second threshold voltage for the second comparator;

wherein signals in the differential output of the second pre-amplifier are applicable to corresponding control inputs in the sets of transistors.

7. The circuitry of claim 6 , wherein the first common mode voltage and the second common mode voltage each vary between low and high values; and

wherein the circuitry further comprises:

a first switch configured to apply the high value or the low value to the first pre-amplifier; and

a second switch configured to apply the high value or the low value to the second pre-amplifier; and

wherein the first and second switches are configured so that the first switch applies the high value to the first pre-amplifier when the second switch applies the low value to the second pre-amplifier, and the second switch applies the high value to the first pre-amplifier when the first switch applies the low value to the second pre-amplifier.

8. The circuitry of claim 6 , further comprising:

a first digital to analog converter configured to receive the differential output of the first pre-amplifier and, in response, to produce a first digital signal; and

a second digital to analog converter configured to receive the differential output of the second pre-amplifier and, in response, to produce a second digital signal.

9. The circuitry of claim 6 , wherein the first amplifier is configured to incorporate the divided voltage into the predefined voltage to produce the threshold voltage; and

wherein the second amplifier is configured to incorporate the second divided voltage into the second predefined voltage to produce the second threshold voltage.

10. The circuitry of claim 1 , wherein the transistors comprise bipolar junction transistors.

11. A digital storage oscillator (DSO) comprising:

an analog to digital converter (ADC) to convert an input analog signal into a digital signal in accordance with a clock signal;

circuitry to generate a trigger signal, the circuitry comprising:

a pre-amplifier having a differential output, wherein the differential output corresponds to a common mode voltage;

a multiplexer comprised of sets of transistors, each transistor having a control input;

a comparator comprising input terminals, a first terminal of the input terminals to receive a signal that is based on an output of the multiplexer, and a second terminal of the input terminals to receive a threshold voltage;

a compensation circuit to produce a divided voltage that varies in accordance with variations in the common mode voltage; and

an amplifier to receive a predefined voltage and to use the divided voltage to affect the predefined voltage to produce the threshold voltage for the comparator;

wherein signals in the differential output of the pre-amplifier are applicable to corresponding control inputs in the sets of transistors;

an edge selector to identify a rising or falling edge of a signal output by the comparator and to produce an asynchronous trigger signal; and

a latch to output the trigger signal based on the asynchronous trigger signal and a version of a clock signal; and

a time interval digitizer to determine a time difference that is based on the asynchronous trigger signal, the time difference being a difference between an actual time that a trigger event occurred and a time that a clock signal running the ADC occurred.

12. The DSO of claim 11 , further comprising:

memory; and

a controller to capture data from the ADC based on the time difference, and to store the data in the memory.

13. The DSO of claim 1 , wherein the sets of transistor comprises two pairs of transistors, each pair of transistors being electrically connected collector-to-collector and emitter-to-emitter.

14. The DSO of claim 11 , wherein the comparator is configured to output a signal in response to the signal received by the comparator exceeding the threshold voltage.

15. The DSO of claim 11 , wherein the amplifier is configured to incorporate the divided voltage into the predefined voltage to produce the threshold voltage.

16. The DSO of claim 11 , wherein the pre-amplifier is a first pre-amplifier, the common mode voltage is a first common mode voltage, the comparator is a first comparator, the amplifier is a first amplifier; and

wherein the circuitry further comprises:

a second pre-amplifier having a differential output, wherein operation of the second preamplifier is responsive to a second common mode voltage;

a second comparator comprising second input terminals, a first terminal of the second input terminals to receive a second signal that is based on a second output of the multiplexer, and a second terminal of the second input terminals to receive a second threshold voltage;

wherein the compensation circuit is configured to produce a second divided voltage that varies in accordance with variations in the second common mode voltage; and

a second amplifier to receive a second predefined voltage and to use the second divided voltage to affect the second predefined voltage to produce the second threshold voltage for the second comparator;

wherein signals in the differential output of the second pre-amplifier are applicable to corresponding control inputs in the sets of transistors.

17. The DSO of claim 16 , wherein the first common mode voltage and the second common mode voltage each vary between low and high values; and

wherein the circuitry further comprises:

a first switch configured to apply the high value or the low value to the first pre-amplifier; and

a second switch configured to apply the high value or the low value to the second pre-amplifier; and

wherein the first and second switches are configured so that the first switch applies the high value to the first pre-amplifier when the second switch applies the low value to the second pre-amplifier, and the second switch applies the high value to the first pre-amplifier when the first switch applies the low value to the second pre-amplifier.

18. A method of driving trigger comparators of a digital storage oscilloscope, the method comprising:

controlling a set of pre-amplifiers so that a differential output from only one of the set of pre-amplifiers is applied to a multiplexer comprised of sets of transistors that are electrically connected to enable the differential output to control application of signals to a set of comparators;

applying a threshold voltage to each comparator in the set of comparators; and

outputting, from each comparator, a signal that is based on a corresponding threshold voltage and a corresponding signal applied as a result of the differential output.

19. The method of claim 18 , wherein the differential output has a common mode voltage; and

wherein the method further comprises:

tracking changes corresponding to the common mode voltage; and

compensating the threshold voltage for the changes.

20. The method of claim 19 , wherein compensating the threshold voltage comprises incorporating, into the threshold voltage, a voltage that corresponds to the changes.