Semiconductor memory integrated device with a precharge circuit having thin-film transistors gated by a voltage higher than a power supply voltage

1. A semiconductor integrated device comprising:

a semiconductor memory circuit; and

a peripheral circuit of the semiconductor memory circuit, wherein

the peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film, and

the semiconductor memory circuit includes:

a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell; and

a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal, and

the activation signal of the precharge circuit is a second voltage higher than the first voltage.

2. The semiconductor integrated device according to claim 1 , wherein the second voltage is used as a word signal that activates the gate transistor of the memory cell.

3. The semiconductor integrated device according to claim 2 , further comprising:

a first driver amplifier that drives the word line; and

a second driver amplifier that drives the activation signal of the precharge circuit,

wherein power supply terminals of the first and second driver amplifiers are each connected to a voltage supply terminal that supplies the second voltage.

4. The semiconductor integrated device according to claim 2 , wherein an activation timing of the word signal is different from an activation timing of the activation signal of the precharge circuit.

5. The semiconductor integrated device according to claim 1 , wherein the pair of bit lines have a precharge voltage substantially equal to one-half of the first voltage.

6. The semiconductor integrated device according to claim 1 , wherein the first voltage is 1.0 V or lower.

7. The semiconductor integrated device according to claim 1 , wherein the second voltage is 1.5 V or lower.

8. The semiconductor integrated device according to claim 1 , wherein

the semiconductor integrated device is configured as one chip, and

the peripheral circuit is a logic circuit that includes an address decoder of the semiconductor memory circuit.

9. The semiconductor integrated device according to claim 1 , wherein the gate transistor includes a transistor having a breakdown voltage substantially equal to that of the first transistor.

10. The semiconductor integrated device according to claim 1 , further comprising a sense amplifier that amplifies a potential difference between the pair of bit lines to the first voltage,

wherein the sense amplifier includes a transistor having a breakdown voltage substantially equal to that of the first transistor.

11. A semiconductor circuit comprising:

a sense amplifier that includes a first transistor, the first transistor being driven by a power supply voltage and having a first oxide film thickness;

a memory cell that includes a second transistor, the second transistor being driven by a first voltage higher than the power supply voltage and having a second oxide film thickness greater than the first oxide film thickness;

a pair of bit lines, one of the pair of bit lines being connected to the memory cell; and

a precharge circuit that sets the pair of bit lines to a predetermined voltage higher than a ground voltage before and after an access to the memory cell,

wherein the precharge circuit includes a transistor driven by the first voltage, and the precharge circuit comprises the first transistor having the first oxide film thickness.