Nonvolatile semiconductor memory
View Patent ↗The invention decreases the number of writing processes of EEPROM. When a mode change signal is L level, a EEPROM is set to a bank mode. In this case, first and second memory banks are independently accessed by a control signal of a first port and a control signal of a second port, respectively. When the mode change signal is H level, the EEPROM is set to a combine mode. In this case, the first and second memory banks are combined into a 4k-bit memory bank, and accessed by the control signal of the first port.
1. A nonvolatile semiconductor memory comprising:
a first memory bank comprising a plurality of electrically writable and readable memory cells;
a second memory bank comprising a plurality of electrically writable and readable memory cells;
a first port to which a first control signal is serially inputted;
a second port to which a second control signal is serially inputted;
a mode change terminal to which a mode change signal is inputted; and
a control circuit selecting a first mode in which an access to the first memory bank is enabled in response to the first control signal and an access to the second memory bank is enabled in response to the second control signal when the mode change signal is at a first level and selecting a second mode in which the access to the first memory bank and the access to the second memory bank are enabled in response to the first control signal when the mode change signal is at a second level,
wherein in the second mode, the first control signal is modified to address both the first memory bank and the second memory bank as one memory.
2. The nonvolatile semiconductor memory of claim 1 , wherein the control circuit comprises a first control circuit controlling the access to the first memory bank, a second control circuit controlling the access to the second memory bank, and a mode change circuit which sends the first control signal to the first control circuit and the second control signal to the second control circuit in the first mode and which sends the first control signal to both the first and second control circuits and disables the second control signal in the second mode.
3. The nonvolatile semiconductor memory of claim 1 , wherein the first control signal comprises a first serial clock and first serial data synchronized with the first serial clock, and the second control signal comprises a second serial clock and second serial data synchronized with the second serial clock.
4. The nonvolatile semiconductor memory of claim 2 , wherein the first control signal comprises a first serial clock and first serial data synchronized with the first serial clock, and the second control signal comprises a second serial clock and second serial data synchronized with the second serial clock.
5. The nonvolatile semiconductor memory of claim 3 , wherein 1-bit address data is added to the first serial data in order to access both the first and second memory banks in the second mode, and the control circuit enables the access to the first memory bank when the added address data is a first value and enables the access to the second memory bank when the added address data is a second value in the second mode.