Dielectric barrier deposition using nitrogen containing precursor
View Patent ↗A process for forming a silicon carbonitride barrier dielectric film between a dielectric film and a metal interconnect of an integrated circuit substrate, comprising the steps of; providing the integrated circuit substrate having a dielectric film; contacting the substrate with a barrier dielectric film precursor comprising: R x R′ y (NR″R ′″ ) z Si wherein R, R ′ , R″ and R′″ are each individually selected from hydrogen, linear or branched saturated or unsaturated alkyl, or aromatic; wherein x÷y+z=4; z=1-3; but R, R ′ cannot both be hydrogen; forming the silicon carbonitride barrier dielectric film with C/Si ratio >0.8 and a N/Si ratio >0.2 on the integrated circuit substrate.
1. A process for forming a silicon carbonitride barrier dielectric film between a dielectric film and a metal interconnect of an integrated circuit substrate, comprising the steps of:
providing the integrated circuit substrate having a dielectric film;
contacting the substrate with a barrier dielectric film precursor selected from the group consisting of bis(isopropylamino)vinylmethylsilane, bis(isopropylamino)divinylsilane, bis(t-butylamino)vinylmethylsilane, bis(t-butylamino)divinylsilane, bis(diethylamino)vinylmethylsilane, bis(diethylamino)divinylsilane, bis(dimethylamino)vinylmethylsilane, bis(dimethylamino)divinylsilane, bis(methylethylamino)vinylmethylsilane, bis(methylethylamino)divinylsilane, bis(isopropylamino)allylmethylsilane, bis(isopropylamino)diallylsilane, bis(t-butylamino)allylmethylsilane, bis(t-butylamino)diallylsilane, bis(diethylamino)allylmethylsilane, bis(diethylamino)diallylsilane, bis(dimethylamino)allylmethylsilane, bis(dimethylamino)diallylsilane, bis(methylethylamino)allylmethylsilane, bis(methylethylamino)diallylsilane, and mixtures thereof; and
forming the silicon carbonitride barrier dielectric film under plasma enhanced chemical vapor deposition conditions, wherein the film has a C/Si ratio >0.8 and a N/Si ratio >0.2 on the integrated circuit substrate,
wherein the silicon carbonitride barrier dielectric film has a density in the range of 1.7 to 2.2 g/cc, and
wherein the silicon carbonitride barrier dielectric film has a K in the range of 4.0 to 4.5.
2. The process of claim 1 wherein a metal interconnect is provided after the forming of the silicon carbonitride barrier dielectric film is formed.
3. The process of claim 1 wherein the silicon carbonitride barrier dielectric film has a compositional gradient of silicon, carbon and nitrogen varied across the depth of the film.
4. A process for forming a silicon carbonitride barrier dielectric film between a dielectric film and a metal interconnect of an integrated circuit substrate, comprising the steps of:
providing the integrated circuit substrate having a dielectric film;
contacting the substrate with a barrier dielectric film precursor comprising bis(isopropylamino)vinylmethylsilane;
wherein no additional nitrogen-containing reactant is used,
wherein the silicon carbonitride barrier dielectric film has a density in the range of 1.7 to 2.2 g/cc, and
wherein the silicon carbonitride barrier dielectric film has a K in the range of 4.0 to 4.5.
5. The process of claim 4 including forming the silicon carbonitride barrier dielectric film with C/Si ratio >0.8 and a N/Si ratio >0.2 on the integrated circuit substrate.
6. A process for forming a silicon carbonitride barrier dielectric film between a dielectric film and a metal interconnect of an integrated circuit substrate, comprising the steps of:
providing the integrated circuit substrate having a dielectric film;
contacting the substrate with a barrier dielectric film precursor comprising bis(isopropylamino)divinylsilane;
wherein no additional nitrogen-containing reactant is used,
wherein the silicon carbonitride barrier dielectric film has a density in the range of 1.7 to 2.2 g/cc, and
wherein the silicon carbonitride barrier dielectric film has a K in the range of 4.0 to 4.5.
7. The process of claim 6 including forming the silicon carbonitride barrier dielectric film with C/Si ratio >0.8 and a N/Si ratio >0.2 on the integrated circuit substrate.