Granted Patent B1

US 7,915,915 · App. 12/772,582 · Granted Mar 29, 2011

Abstract

Claims (31)

1. Circuitry comprising

a differential stage coupled to receive a data signal;

a current source configured to supply a current to the differential stage;

an enabling element coupled to control activation and deactivation of the current source; and

a compensation circuit configured to provide a compensation pulse to the current source when the current source is activated.

2. Circuitry of claim 1 , wherein the compensation circuit comprises a capacitor to provide the compensation pulse.

3. Circuitry of claim 1 , wherein the current source comprises a current mirror, and wherein the enabling element is configured to activate or deactivate the current mirror's functionality in response to an enable signal.

4. Circuitry of claim 3 , wherein the enabling element comprises an enable transistor, and wherein the enable signal is adapted to render the enable transistor conductive or non-conductive.

5. Circuitry of claim 2 , wherein the compensation circuit further comprises a resistor divider circuit, the capacitor being coupled between the current source and the divider bridge.

6. Circuitry of claim 1 , wherein the compensation circuit comprises a capacitance divider coupled to the current source (N 3 , N 4 ).

7. Circuitry of claim 2 , wherein the compensation circuit further comprises an additional current source, the capacitor being coupled between the additional current source and the current source.

8. A semiconductor device comprising

first and second transistors coupled to a common node to function as a differential circuit;

first and second nodes supplied respectively with a bias voltage and a control signal;

third and fourth transistors coupled in series between the common node and a reference potential node, the third transistor including a control electrode electrically coupled to the first node, the fourth transistor including a control electrode electrically coupled to the second node; and

a capacitor electrically coupled between the control electrode of the third transistor and the second node.

9. The device as claimed in claim 8 , further comprising a first resistor coupled between the capacitor and the second node and a second resistor coupled between the capacitor and the reference potential node.

10. The device as claimed in claim 9 , further comprising a first inverter coupled between the second node and the control electrode of the third transistor and a second inverter coupled between the second node and the first resistor.

11. The device as claimed in claim 8 , wherein the capacitor is a first capacitor and the device further comprises a second capacitor coupled between the first node and the reference potential node.

12. The device as claimed in claim 11 , further comprising a first inverter coupled between the second node and the control electrode of the third transistor and a second inverter coupled between the second node and the first capacitor.

13. The device as claimed in claim 8 , wherein further comprising a switch circuit inserted between the capacitor and the second node and a resistive element coupled between the capacitor and the reference potential node, the switch being rendered conductive when the third transistor rendered conductive.

14. The device as claimed in claim 13 , wherein the switch circuit comprises a current source and a fifth transistor including a control electrode coupled to the second node and a source-drain path coupled between the current source and the capacitor.

15. The device as claimed in claim 14 , wherein each of the first to fourth transistor is of a first channel type and the fifth transistor is of a second channel type.

16. The device as claimed in claim 14 , further comprising an inverter coupled between the second node and the control electrode of the third transistor.

17. A method comprising:

providing a circuit which comprises first and second transistors functioning as a differential circuit, a third transistor supplied at a control electrode thereof with a bias voltage to function as a current source for the differential circuit, and fourth transistor functioning as a switch for the current source;

supplying a control signal to the fourth transistor to being the fourth transistor from a non-conductive state to a conductive; and

boosting a voltage level at a control electrode of the third transistor in response to the third transistor being brought from the non-conductive to the conductive state.

18. The method as claimed in claim 17 , wherein the boosting the voltage level comprises charging a capacitor when the third transistor is in the non-conductive state and adding charges of the capacitor to the bias voltage.

19. The method as claimed in claim 18 , wherein charging the capacitor comprises supplying one end of the capacitor with a signal related to the control signal and supplying the other end of the capacitor with the bias voltage.

20. The method as claimed in claim 18 , wherein charging the capacitor comprises supplying one end of the capacitor with a reference voltage and supplying the other end of the capacitor with the bias voltage when the third transistor is in the non-conductive state.

Assignments (8)