DELAY CIRCUIT
A delay circuit ( 100 ) includes capacitor elements constituted of nMOS transistors ( 141, 142 ) between an input inverter circuit ( 110 ) and an output inverter circuit ( 120 ). The input inverter circuit ( 110 ) includes a pMOS transistor (PM 1 ) and an nMOS transistor (NM 1 ) that are directly connected between a power source potential (VDD) and a ground potential (VSS) through a resistor (R 1 ). Between a signal line ( 130 ) and the gate of the nMOS transistor ( 141 ), and between the signal line ( 130 ) and the gate of the nMOS transistor ( 142 ), pMOS transistors ( 151, 152 ) are provided, respectively. In this structure, in the case where an input signal is changed from L to H, the PVT sensitivity of a delay circuit is automatically alleviated. As a result, the PVT sensitivity is automatically alleviated.
1 . A delay circuit comprising:
an input inverter circuit that includes a drive transistor connected to a first power source, an input signal being inputted to the input inverter circuit;
an output inverter circuit that has an input node to which a delay control node that is an output terminal of the input inverter circuit is connected through a signal line;
a capacitor element that is connected between the signal line and a second power source; and
a switch transistor that is provided between the signal line and the capacitor element,
wherein the drive transistor and the switch transistor are semiconductor transistors that have the same conductivity type.
2 . The delay circuit according to claim 1 , wherein
the first power source is a high-voltage side power source,
the second power source is a low-voltage side power source, and
the drive transistor and the switch transistor are P-type semiconductor transistors.
3 . The delay circuit according to claim 1 , wherein
the first power source is a low-voltage side power source;
the second power source is a high-voltage side power source; and
the drive transistor and the switch transistor are N-type semiconductor transistors.
4 . The delay circuit according to claim 1 , wherein
a plurality of sets of the capacitor element and the switch transistor is provided between the input inverter circuit and the output inverter circuit, and
the switch transistor is subjected to a selective on/off control in accordance with an amount of delay adjustment of the delay circuit.
5 . The delay circuit according to claim 1 , wherein the capacitor element is formed of a semiconductor transistor whose conductivity type is opposite to that of the switch transistor.
6 . A delay circuit comprising:
a first transistor that has a first conductivity type and has a contact point set to a predetermined potential;
a second transistor that has the first conductivity type and is connected to the contact point; and
a first capacity element that is connected to the second transistor, the first capacitor element having a variable load state with respect to the contact point in accordance with a potential difference between a gate potential of the second transistor and the potential of the contact point.
7 . The delay circuit according to claim 6 , wherein the capacitor element is formed of a third transistor whose conductivity type is opposite to that of the first transistor.
8 . The delay circuit according to claim 6 , further comprising:
a fourth transistor that that has the same conductivity type as that of the second transistor and is connected to the contact point; and
a second capacitor element that is connected to the first transistor.
9 . The delay circuit according to claim 8 , wherein the second capacitor element is formed of a fifth transistor that has a conductivity type opposite to that of the first transistor.
10 . The delay circuit according to claim 6 , further comprising a sixth transistor that has a conductivity type opposite to the first conductivity type and is connected to the contact point,
wherein the first transistor and the sixth transistor constitute an inverter circuit.
11 . The delay circuit according to claim 10 , further comprising a resistor element between the contact point and the sixth transistor.
12 . The delay circuit according to claim 8 , wherein a gate potential of the second transistor and a gate potential of the fourth transistor are each set to a complementary potential.