IP Library Granted Patent US 8,503,189
Granted Patent B2
US 8,503,189 · App. 12/773,128 · Granted Aug 6, 2013

Pb-free solder-connected structure and electronic device

Inventors: Hanae Shimokawa (Yokohama, JP); Tasao Soga (Fujisawa, JP); Hiroaki Okudaira (Yokohama, JP); Toshiharu Ishida (Fujisawa, JP); Tetsuya Nakatsuka (Yokohama, JP); Yoshiharu Inaba (Tachikawa, JP); Asao Nishimura (Kokubunji, JP)
Assignee: Renesas Electronics Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,503,189
App. No.
12/773,128
Granted
Aug 6, 2013
Kind
B2
Abstract

Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.

Claims (15)

1. A semiconductor device to be mounted on a substrate via a Pb-free solder, comprising:

a lead; and

a Bi-containing layer formed on the lead and constituted by an alloy consisting essentially of Sn and Bi,

wherein a contained amount of Bi in the alloy is greater than or equal to 1 wt %, and less than or equal to 5 wt %; and

wherein the Bi-containing layer is a layer separate from the Pb-free solder.

2. The semiconductor device according to claim 1 , wherein the lead is comprised of a Cu alloy.

3. The semiconductor device according to claim 1 , wherein the lead is comprised of a Fe—Ni alloy.

4. The semiconductor device according to claim 1 , wherein the semiconductor device is a Thin Small Outline Package (TSOP).

5. The semiconductor device according to claim 1 , wherein the semiconductor device is a Quad Flat Package (QFP).

6. The semiconductor device according to claim 1 , wherein the Bi-containing layer is formed directly on the lead.

7. The semiconductor device according to claim 3 , wherein a Cu layer is formed between the lead and the Bi-containing layer.

8. The semiconductor device according to claim 1 , wherein the lead contains Cu.

9. The semiconductor device according to claim 1 , wherein the Bi-containing layer is a layer in addition to the Pb-free solder.

10. The semiconductor device according to claim 1 , which additionally includes a Pb-free solder, the Bi-containing layer being provided between the lead and the Pb-free solder.

11. The semiconductor device according to claim 1 , wherein the Bi-containing layer is a layer that improves wettability of the Pb-free solder to the lead.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
MERGER/CHANGE OF NAME Recorded Feb 22, 2013
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 029854/0887 →
Priority Claims (1)
JP 9-346811 · Dec 16, 1997 · national
Continuity (4)
Continuation 11331220 · Jan 13, 2006
Division 09971566 · Oct 9, 2001
Division 09581631
Related Publication 20100214753A1 · Aug 26, 2010