IP Library Granted Patent US 8,350,606
Granted Patent B2
US 8,350,606 · App. 12/776,906 · Granted Jan 8, 2013

Delay circuit

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Quick Facts
Patent No.
US 8,350,606
App. No.
12/776,906
Granted
Jan 8, 2013
Kind
B2
Abstract

In a delay circuit for inputting square waves, fluctuations in the amount of delay brought about by noise pulses present in input signals are reduced. A switch (SW 3 ) is controlled by an output signal (Vdo) from a Schmitt comparator, and selects either an electric current source for supplying a charging current to a capacitor (Cst) or an electric current source for supplying a discharging current. A current supply from the selected electric current source is turned on/off by controlling switches (SW 1 , SW 2 ) using an input signal (Vdi). The Schmitt comparator switches the level of Vdo in accordance with a voltage of Cst. The charging current is supplied to Cst when Vdi is H level at rising edge of Vdi, and the discharging current is supplied to Cst when Vdi is L level at trailing edge of Vdi.

Claims (13)

1. A delay circuit for delaying and switching the level of an output signal relative to the switching between two levels in a single input signal, wherein:

in a period in which the output signal is at a first output level correlated with a first input level of the input signal, a predetermined quantity to be evaluated is increased according to an integrated value of a period in which the input signal is at a second input level, and the output signal is switched from the first output level to the second output level when the quantity to be evaluated exceeds a predetermined upper threshold; and

in a period in which the output signal is at a second output level correlated with the second input level, the quantity to be evaluated is reduced according to the integrated value of a period in which the input signal is at a first input level, and the output signal is switched from the second output level to the first output level when the quantity to be evaluated declines below a lower threshold set lower than the upper threshold.

2. The delay circuit of claim 1 , comprising:

a Schmitt trigger comparator for setting the upper threshold and the lower threshold for an input voltage, and outputting the output signal;

a capacitor for inputting a voltage that corresponds to an amount of charge to the Schmitt trigger comparator; and

a charge/discharge circuit for alternatively outputting a charging current to charge the capacitor and a discharging current to discharge the capacitor; wherein the charge/discharge circuit selectively outputs the charging current in a period in which the output signal is at the first output level and the input signal is at the second input level; and

wherein the charge/discharge circuit selectively outputs the discharging current in a period in which the output signal is at the second output level and the input signal is at the first input level.

3. The delay circuit of claim 2 , the charge/discharge circuit having:

a charging current source for generating the charging current; a discharging current source for generating the discharging current;

a charge/discharge selection switch provided between the capacitor and the charging current source and discharging current source, and used to connect the charging current source and the capacitor in a period in which the output signal is at the first output level, and to connect the discharging current source and the capacitor in a period in which the output signal is at the second output level;

a charge control switch connected in series between the charging current source and the charge/discharge selection switch, and used to selectively establish an on-state in a period in which the input signal is at the second input level; and

a discharge control switch connected in series between the discharging current source and the charge/discharge switch, and used to selectively establish the on-state in a period in which the input signal is at the first input level.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033813 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 21, 2015
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034816/0510 →
CHANGE OF NAME Recorded Dec 3, 2014
From: SANYO SEMICONDUCTOR CO., LTD
To: SYSTEM SOLUTIONS CO., LTD.
Reel/Frame 034537/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033813/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →