Gate driver for enhancement-mode and depletion-mode wide bandgap semiconductor JFETs
View Patent ↗A DC-coupled two-stage gate driver circuit for driving a junction field effect transistor (JFET) is provided. The JFET can be a wide bandgap junction field effect transistor (JFET) such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit and a pull-down circuit. The driver is configured to accept an input pulse-width modulation (PWM) control signal and generate an output driver signal for driving the gate of the JFET.
1. A two-stage gate driver circuit for driving a junction field effect transistor (JFET) having a gate, a source and a drain, comprising:
an input for supplying a control pulse signal V in ;
three resistors, R 1 , R 2 and R 3 , each having first and second terminals and being directly electrically coupled to the gate of the JFET by the second terminal;
a first turn-on circuit electrically coupled between the input and the first terminal of the resistor R 2 ;
a second turn-on circuit electrically coupled between the input and the first terminal of the resistor R 1 ; and
a pull-down circuit electrically coupled between the input and the first terminal of the resistor R 3 .
2. The two-stage gate driver circuit of claim 1 , wherein the control pulse signal V in , is configured to have a pulse duration, t on , and a pulse-off duration, t off , such that in the pulse duration t on , the JFET is in a conduction state, while the JFET is in a blocking state in a pulse-off duration t off .
3. A two-stage gate driver circuit for driving a junction field effect transistor (JFET) having a gate, a source and a drain, comprising:
an input for supplying a control pulse signal V in ;
three resistors, R 1 , R 2 and R 3 , each having first and second terminals and being electrically coupled to the gate of the JFET by the second terminal;
a first turn-on circuit electrically coupled between the input and the first terminal of the resistor R 2 ;
a second turn-on circuit electrically coupled between the input and the first terminal of the resistor R 1 ; and
a pull-down circuit electrically coupled between the input and the first terminal of the resistor R 3 ,
wherein the control pulse signal V in is configured to have a pulse duration, t on , and a pulse-off duration, t off , such that in the pulse duration t on , the JFET is in a conduction state, while the JFET is in a blocking state in a pulse-off duration t off and,
wherein the first turn-on circuit comprises:
a switch S 1 having a gate, a source electrically coupled to the first terminal of the resistor R 2 and a drain electrically coupled to a first current source for providing a positive voltage +V 1 ; and
a pulse generator electrically coupled between the input and the gate of the switch S 1 .
4. The two-stage gate driver circuit of claim 3 , wherein the second turn-on circuit comprises a switch S 2 having a gate electrically coupled to the input, a source electrically coupled to the first terminal of the resistor R 1 and a drain electrically coupled to a second current source for providing a positive voltage +V 2 .
5. The two-stage gate driver circuit of claim 4 , wherein the first and second current sources are corresponding to a single current source or two different current sources.
6. The two-stage gate driver circuit of claim 4 , wherein the pull-down circuit comprises a switch S 3 having a gate electrically coupled to the input, a source electrically coupled to a third current source for providing a negative voltage −V 3 and a drain electrically coupled to the first terminal of the resistor R 3 .
7. The two-stage gate driver circuit of claim 6 , wherein the pull-down circuit further comprises an inverter electrically coupled between the input and the gate of the switch S 3 .
8. The two-stage gate driver circuit of claim 7 , wherein when the control pulse signal V in is supplied:
the pulse generator responsively generates a corresponding control pulse signal, V c2 , having a pulse duration, t 1 , that turns on the switch S 1 for the pulse duration t 1 ;
the control pulse signal V in turns on the switch S 2 for the pulse duration t on and turns off the switch S 2 for the pulse duration t off , respectively; and
the control pulse signal V in turns off the switch S 3 for the pulse duration t on and turns on the switch S 3 for the pulse duration t off , respectively.
9. The two-stage gate driver circuit of claim 8 , wherein the generated control pulse signal V c2 is in synchronization with the control pulse signal and wherein the pulse duration, t 1 of the generated control pulse signal V c2 is equal to or less than 15% of the pulse duration t on of the control pulse signal V in .
10. The two-stage gate driver circuit of claim 9 , wherein the pulse duration t 1 of the generated control pulse signal V c2 is adjustable manually.
11. The two-stage gate driver circuit of claim 9 , wherein, the pulse duration t 1 of the generated control pulse signal V c2 is adjustable automatically in accordance with a feedback signal, V FB , from the JFET.
12. A two-stage gate driver circuit for driving a junction field effect transistor (JFET) having a gate, a source and a drain, comprising:
an input for supplying a control pulse signal V in , wherein the control pulse signal V in is configured to have a pulse duration, t on , and a pulse-off duration, t off , such that the JFET is in a conduction state in the pulse duration t on , while the JFET is in a blocking state in the pulse-off duration t off ;
a first turn-on circuit, wherein the first turn-on circuit comprises:
a switch S 1 having a gate, a source electrically coupled to the gate of the JFET through a resistor R 2 and a drain electrically coupled to a first current source for providing a positive voltage +V 1 ; and
a pulse generator electrically coupled between the input and the gate of the switch Sl, wherein the pulse generator is configured such that when the control pulse signal V in is supplied, the pulse generator responsively generates a corresponding control pulse signal, V c2 , that is in synchronization with the control pulse signal V in ;
a second turn-on circuit; and
a pull-down circuit,
wherein the first turn-on circuit, the second turn-on circuit and the pull-down circuit are electrically coupled between the input and the gate of the JFET in parallel; and
wherein the generated control pulse signal V c2 has a pulse duration, t 1 , that is equal to or less than 15% of the pulse duration t on of the control pulse signal V in .
13. The two-stage gate driver circuit of claim 12 , wherein the pulse duration t 1 of the generated control pulse signal V c2 is adjustable manually.
14. The two-stage gate driver circuit of claim 12 , wherein, the pulse duration t 1 of the generated control pulse signal V c2 is adjustable automatically in accordance with a feedback signal, V FB , from the JFET.
15. The two-stage gate driver circuit of claim 12 , wherein the second turn-on circuit comprises a switch S 2 having a gate electrically coupled to the input, a source electrically coupled to the gate of the JFET through a resistor R 1 and a drain electrically coupled to a second current source for providing a positive voltage +V 2 .
16. The two-stage gate driver circuit of claim 15 , wherein the pull-down circuit comprises:
a switch S 3 having a gate, a source electrically coupled to a third current source for providing a negative voltage −V 3 and a drain electrically coupled to the gate of the JFET through a resistor R 3 ; and
an inverter electrically coupled between the input and the gate of the switch S 3 .
17. The two-stage gate driver circuit of claim 12 , wherein the first turn-on circuit is electrically coupled between a first current source and the gate of the JFET through a resistor R 2 , wherein the first current source is adapted for providing a positive voltage, +V 1 .
18. The two-stage gate driver circuit of claim 17 , wherein in operation, when the control pulse signal V in is in the pulse duration t on , the first turn-on circuit is turned on for a duration, t 1 , that is equal to or less than 15% of the pulse duration t on of the control pulse signal V in , while the first turn-on circuit is turned off for the pulse-off duration t off when the control pulse signal V in is in the pulse-off duration t off .
19. The two-stage gate driver circuit of claim 18 , wherein the second turn-on circuit is electrically coupled between a second current source and the gate of the JFET through a resistor R 1 , wherein the resistance of R 2 is greater than the resistance of R 1 , and wherein the second current source is adapted for providing a positive voltage, +V 2 .
20. The two-stage gate driver circuit of claim 19 , wherein the first and second current sources are corresponding to a single current source or two different current sources.
21. The two-stage gate driver circuit of claim 19 , wherein in operation, when the control pulse signal V in is in the pulse duration t on , the second turn-on circuit is turned on for the pulse duration t on , while the second turn-on circuit is turned off for the pulse-off duration t off when the control pulse signal V in is in the pulse-off duration t off .
22. The two-stage gate driver circuit of claim 19 , wherein the pull-down circuit is electrically coupled between a third current source and the gate of the JFET through a resistor R 3 , wherein the third current source is adapted for providing a negative voltage −V 3 .
23. The two-stage gate driver circuit of claim 22 , wherein the pull-down circuit comprises an inverter electrically coupled between the input and the resistor R 3 .
24. The two-stage gate driver circuit of claim 23 , wherein the pull-down circuit is turned off for the pulse duration t on when the control pulse signal V in is in the pulse duration t on and wherein the pull-down circuit is turned on for the pulse duration t off when the control pulse signal V in is in the pulse-off duration t off .
25. The two-stage gate driver circuit of claim 1 , wherein the JFET is a wide bandgap JFET or a SiC JFET.
26. The two-stage gate driver circuit of claim 12 , wherein the JFET is a wide bandgap JFET or a SiC JFET.
27. The two-stage gate driver circuit of claim 3 , wherein each of the three resistors, R 1 , R 2 and R 3 , is directly electrically coupled to the gate of the JFET by the second terminal.