BUS ARBITRATION CIRCUIT AND BUS ARBITRATION METHOD

1 . A bus arbitration circuit comprising:

a fixed priority determination circuit that grants a bus use right to an access request from a higher priority bus master among access requests from a plurality of bus masters; and

a determination adjustment circuit that determines whether or not to assert the access request from the plurality of bus masters to the fixed priority determination circuit,

wherein the determination adjustment circuit includes a mask circuit that masks an access request from a bus master which is granted the bus use right, for a given period of time, when the access request from the bus master which is granted the bus use right and an access request from a bus master which is not granted the bus use right compete with each other.

2 . The bus arbitration circuit according to claim 1 , wherein the given period of time in which the mask circuit masks the access request from the bus masters is a period of time until the fixed priority determination circuit completes a bus arbitration processing for granting the bus use right to a subsequent bus master.

3 . The bus arbitration circuit according to claim 1 , wherein the determination adjustment circuit recognizes the bus master granted the bus use right based on bus grant signals output from the fixed priority determination circuit to the plurality of bus masters so as to grant the bus use right.

4 . The bus arbitration circuit according to claim 1 , wherein

the determination adjustment circuit includes a comparison circuit that compares the bus grant signals output to the plurality of bus masters, and

the comparison circuit outputs a mask signal to the mask circuit based on a comparison result of the bus grant signals.

5 . The bus arbitration circuit according to claim 1 , wherein the determination adjustment circuit masks the access request from the bus masters when a period of time in which the fixed priority determination circuit continuously grants the bus use right reaches a given period of time.

6 . The bus arbitration circuit according to claim 5 , wherein the period of time in which the fixed priority determination circuit continuously grants the bus use right corresponds to a bus cycle of a bus master granted the bus use right.

7 . The bus arbitration circuit according to claim 5 , wherein the period of time in which the access request from the bus masters is masked is a given period of time corresponding to a bus cycle of a bus master whose access request is masked.

8 . The bus arbitration circuit according to claim 5 , wherein the period of time in which the fixed priority determination circuit continuously grants the bus use right and the period of time in which the mask circuit masks the access request from the bus masters can be set for each of the plurality of bus masters.

9 . The bus arbitration circuit according to claim 5 , wherein the determination adjustment circuit includes:

a mask register that stores a set value of a period of time in which the access request from the bus masters is masked;

a cycle register that stores a set value of a period of time in which the fixed priority determination circuit can continuously grant the bus use right;

a cycle counter that counts a value corresponding to a mask period in which the access request from the bus masters is masked and a value corresponding to a use grant period in which the fixed priority determination circuit continuously grants the bus use right; and

a comparison circuit that compares the set value stored in the mask register with the value corresponding to the mask period counted by the cycle counter, and compares the set value stored in the cycle register with the value corresponding to the use grant period counted by the cycle counter.

10 . A bus arbitration method that arbitrates access requests from a plurality of bus masters, comprising:

detecting a state of competition between an access request from a bus master which is granted a bus use right and an access request from a bus master which is not granted the bus use right;

masking the access request from the bus master which is granted the bus use right, for a given period of time, when the access request from the bus master which is granted the bus use right and the access request from the bus master which is not granted the bus use right compete with each other; and

granting the bus use right to an access request from a higher priority bus master when there are a plurality of access requests from bus masters which are not granted the bus use right.

11 . The bus arbitration method according to claim 10 , wherein the given period of time in which the access request from the bus master is masked is a period of time until a bus arbitration processing for granting the bus use right to a subsequent bus master is completed.

12 . The bus arbitration method according to claim 10 , further comprising recognizing a bus master granted the bus use right based on bus grant signals output to the plurality of bus masters so as to grant the bus use right.

13 . The bus arbitration method according to claim 10 , wherein the access request from the bus masters is masked when a period of time in which the bus use right is continuously granted reaches a given period of time.

14 . The bus arbitration method according to claim 13 , wherein the period of time in which the bus use right is continuously granted corresponds to a bus cycle of the bus master granted the bus use right.

15 . The bus arbitration method according to claim 13 , wherein the period of time in which the access request from the bus masters is masked is a given period of time corresponding to a bus cycle of the bus master whose access request is masked.

16 . The bus arbitration method according to claim 13 , wherein the period of time in which the bus use right is continuously granted and the period of time in which the access request from the bus masters is masked can be set for each of the plurality of bus masters.