Clock distribution circuit and layout design method using same

1. A layout design method for a clock tree circuit, comprising:

disposing a first clock distribution circuit in a clock tree circuit;

wiring the clock tree circuit in which the first clock distribution circuit is disposed;

verifying timing of the wired clock tree circuit; and

replacing the first distribution element by one of a plurality of second clock distribution circuits based on a result of the timing verification, all of the plurality of second clock distribution circuits having roughly a same input load capacitance as the first clock distribution circuit and different delay values from the first clock distribution circuit.

2. The layout design method according to claim 1 , further comprising verifying timing of the clock tree circuit in which the replacement to the one of the plurality of second clock distribution circuits was made.

3. The layout design method according to claim 1 , wherein the first clock distribution circuit has roughly a middle delay value among a plurality of prepared clock distribution circuits.

4. The layout design method according to claim 3 , wherein a rising time and a falling time of the first clock distribution circuit are roughly equal.

5. The layout design method according to claim 1 , wherein in the replacement, a pulse width calculated from a result of the timing verification is compared with a desired pulse width, and the one of the plurality of second clock distribution circuits is selected based on their difference.

6. The layout design method according to claim 1 , wherein

each of the first and second clock distribution circuits comprises a first inverter circuit, the first inverter circuit comprising:

serially-connected N transistors having a first conductive type (N is a natural number equal to or greater than 2); and

M transistors having a second conductive type (M is a natural number equal to or greater than 1), the M transistors being connected in series with the N transistors having the first conductive type, and

wherein the first and second clock distribution circuits are different in a combination of a pair of a transistor having the first conductive type and a transistor having the second conductive type of which an input signal is input to a control terminal.

7. The layout design method according to claim 6 , wherein transistor sizes of the transistors having the first and second conductive types are determined so that a rising time and a falling time become roughly equal in the combination that provides the roughly middle delay value.

8. A clock distribution circuit comprising a first inverter circuit, the first inverter circuit comprising:

serially-connected N transistors having a first conductive type (N is a natural number equal to or greater than 2); and

M transistors having a second conductive type (M is a natural number equal to or greater than 1), the M transistors being connected in series with the N transistors having the first conductive type,

wherein a delay value is adjusted by a combination of a pair of a transistor having the first conductive type and a transistor having the second conductive type of which an input signal is input to a control terminal, and

wherein the input load capacitance remains roughly the same regardless of the adjusted delay value.

9. The clock distribution circuit according to claim 8 , further comprising a second inverter connected in series with the first inverter.