IP Library Granted Patent US 8,198,674
Granted Patent B2
US 8,198,674 · App. 12/781,484 · Granted Jun 12, 2012

Semiconductor device and manufacturing method thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,198,674
App. No.
12/781,484
Granted
Jun 12, 2012
Kind
B2
Abstract

To provide a semiconductor device including a first silicon pillar, an interlayer dielectric film provided on an upper surface of the first silicon pillar and having a through-hole filled with a conductive material, and a first-diffusion-layer contact plug provided on an upper-side opening of the through-hole. An area of a lower-side opening of the through-hole is equal to an area of the upper surface of the first silicon pillar, and an area of the upper-side opening of the through-hole is larger than the area of the lower-side opening of the through-hole. With this configuration, an area of a contact surface between the conductive material within the through-hole and the first-diffusion-layer contact plug is larger than the area of the upper surface of the first silicon pillar.

Claims (23)

1. A semiconductor device comprising:

a substrate;

a first silicon pillar projecting substantially perpendicularly with respect to a main surface of the substrate;

an interlayer dielectric film that covers the main surface of the substrate, the interlayer dielectric film having a through-hole into which a conductive material is buried, the through-hole having a lower-side opening that exposes an upper surface of the first silicon pillar and an upper side opening;

a first diffusion layer formed in or neighboring an upper part of the first silicon pillar;

a second diffusion layer formed in or neighboring a lower part of the first silicon pillar;

a first-diffusion-layer contact plug provided on the upper-side opening of the through-hole so as to contact the conductive material within the through-hole; and

a gate electrode that covers a side surface of the first silicon pillar via a first gate dielectric film, wherein

an area of the lower-side opening of the through-hole is substantially equal to an area of the upper surface of the first silicon pillar,

an area of the upper-side opening of the through-hole is larger than the area of the lower-side opening of the through-hole, and

an area of a contact surface between the conductive material within the through-hole and the first-diffusion-layer contact plug is larger than the area of the upper surface of the first silicon pillar.

2. The semiconductor device as claimed in claim 1 , wherein an area of a cross section parallel to the main surface at a relatively upper position of the through-hole is larger than an area of a cross section parallel to the main surface at a relatively lower position of the through-hole.

3. The semiconductor device as claimed in claim 1 , wherein a center of the through-hole and a center of the first silicon pillar match each other as viewed from perpendicular direction with respect to the main surface of the substrate.

4. The semiconductor device as claimed in claim 1 , further comprising a sidewall dielectric film that covers an inner wall of the through-hole.

5. The semiconductor device as claimed in claim 1 , wherein the conductive material within the through-hole serves as the first diffusion layer.

6. The semiconductor device as claimed in claim 1 , further comprising:

a second silicon pillar parallel to the first silicon pillar;

a cap insulation film that covers an upper part of the second silicon pillar; and

a gate contact plug, wherein

the gate electrode also covers a side surface of the second silicon pillar via a second gate dielectric film, and

the gate contact plug is connected to the upper surface of the gate electrode that is positioned at a part of a periphery of the second silicon pillar.

7. The semiconductor device as claimed in claim 6 , wherein the interlayer dielectric film comprises a silicon oxide, and the cap insulation film comprises a silicon nitride.

8. The semiconductor device as claimed in claim 1 , further comprising a second-diffusion-layer contact plug connected to the second diffusion layer.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2010
From: IKEBUCHI, YOSHINORI
To: ELPIDA MEMORY, INC.
Reel/Frame 024395/0674 →