DISPLAY APPARATUS AND METHOD OF TESTING THE SAME
A display apparatus includes a delay generation circuit that generates a reference signal and a competing signal, the competing signal being generated based on a delay set signal, an input order judgment circuit that judges an input order of the reference signal and the competing signal, a delay set circuit that generates the delay set signal based on a judgment result in the input order judgment circuit, and an internal synchronous control circuit that controls transfer of display data between a CPU and a display panel. An operation test of the internal synchronous control circuit is performed using the reference signal and the competing signal. Hence, fault coverage can be enhanced.
1 . A display apparatus comprising:
a delay generation circuit that generates a reference signal and a competing signal, the competing signal being generated based on a delay set signal;
an input order judgment circuit that judges an input order of the reference signal and the competing signal;
a delay set circuit that generates the delay set signal based on a judgment result in the input order judgment circuit; and
an internal synchronous control circuit that controls transfer of display data between a CPU and a display panel, wherein
an operation test of the internal synchronous control circuit is performed using the reference signal and the competing signal.
2 . The display apparatus according to claim 1 , wherein, when a timing of rising of the reference signal is earlier than a timing of rising of the competing signal, the delay set circuit generates the delay set signal to advance the timing of rising of the competing signal.
3 . The display apparatus according to claim 1 , wherein, when a timing of rising of the reference signal is later than a timing of rising of the competing signal, the delay set circuit generates the delay set signal to delay the timing of rising of the competing signal.
4 . The display apparatus according to claim 1 , wherein the delay set circuit generates the delay set signal so as to gradually advance the timing of rising of the competing signal from the latest timing of rising.
5 . The display apparatus according to claim 1 , wherein the delay set circuit generates the delay set signal so as to gradually delay the timing of rising of the competing signal from the earliest timing of rising.
6 . The display apparatus according to claim 4 , wherein the operation test of the internal synchronous control circuit is terminated at a timing at which the input order of the reference signal and the competing signal is switched.
7 . The display apparatus according to claim 5 , wherein the operation test of the internal synchronous control circuit is terminated at a timing at which the input order of the reference signal and the competing signal is switched.
8 . The display apparatus according to claim 1 , wherein the delay generation circuit includes a delay element group and a multi-input selector, and the multi-input selector selects any one of outputs of the delay element group based on the delay set signal to generate the competing signal.
9 . The display apparatus according to claim 1 , wherein the reference signal is corresponding to a control signal that controls transfer of the display data between the CPU and a memory, and the competing signal is corresponding to a control signal that controls transfer of the display data from the memory to the display panel.
10 . The display apparatus according to claim 1 , wherein the reference signal is corresponding to a control signal that controls transfer of the display data from a memory to the display panel, and the competing signal is corresponding to a control signal that controls transfer of the display data between the CPU and the memory.
11 . An operation test method of a display apparatus including an internal synchronous control circuit, the circuit controlling transfer of display data between a CPU and a display panel, the operation test method comprising:
generating a reference signal and a competing signal;
judging an input order of the reference signal and the competing signal;
generating the delay set signal based on judgment result of the input order;
generating the competing signal based on the delay set signal; and
executing an operation test of the internal synchronous control circuit using the reference signal and the competing signal.
12 . The operation test method of the display apparatus according to claim 9 , wherein, when a timing of rising of the reference signal is earlier than a timing of rising of the competing signal, the timing of rising of the competing signal is advanced.
13 . The operation test method of the display apparatus according to claim 9 , wherein, when a timing of rising of the reference signal is later than a timing of rising of the competing signal, the timing of rising of the competing signal is delayed.
14 . The operation test method of the display apparatus according to claim 9 , wherein the delay set signal is generated so as to gradually advance the timing of rising of the competing signal from the latest timing of rising.
15 . The operation test method of the display apparatus according to claim 9 , wherein the delay set signal is generated so as to gradually delay the timing of rising of the competing signal from the earliest timing of rising.
16 . The operation test method of the display apparatus according to claim 12 , wherein the operation test of the internal synchronous control circuit is terminated at a timing at which the input order of the reference signal and the competing signal is switched.
17 . The operation test method of the display apparatus according to claim 13 , wherein the operation test of the internal synchronous control circuit is terminated at a timing at which the input order of the reference signal and the competing signal is switched.