IP Library Granted Patent US 8,063,690
Granted Patent B2
US 8,063,690 · App. 12/786,761 · Granted Nov 22, 2011

Level shift circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,063,690
App. No.
12/786,761
Granted
Nov 22, 2011
Kind
B2
Abstract

The invention provides a level shift circuit that prevents an offset when the supply voltage changes. A level shift circuit has a differential amplification circuit, a current generation circuit, a capacitor and a holding circuit. An input signal from the optical pickup is inputted to the non-inversion input terminal of the differential amplification circuit. First, by turning on a first switch, a feedback loop is formed by the differential amplification circuit, the current generation circuit and the capacitor to perform a level shift, and the voltage charged in the capacitor is held by the holding circuit. Then by turning off the first switch and turning on a second switch, the voltage held by the holding circuit is applied to the non-inversion input terminal of the differential amplification circuit to perform a level shift.

Claims (10)

1. A level shift circuit comprising:

a differential amplification circuit comprising an inversion input terminal, a non-inversion input terminal and an output terminal, the inversion input terminal receiving a reference voltage, the non-inversion input terminal receiving an input signal and the output terminal outputting an output signal;

a feedback resistor connected between the output terminal and the inversion input terminal of the differential amplification circuit;

a current generation circuit generating an electric current corresponding to a difference voltage between the reference voltage and the output signal of the differential amplification circuit;

a capacitor connected to an output terminal of the current generation circuit so as to be charged with the electric current generated by the current generation circuit to induce a voltage in the capacitor;

a holding circuit generating and holding the induced voltage in the capacitor; and

a switching circuit switching from a first state where the voltage induced in the capacitor is applied to the non-inversion input terminal of the differential amplification circuit to a second state where the voltage held in the holding circuit is applied to the non-inversion input terminal of the differential amplification circuit,

wherein the holding circuit comprises a counter, a DA converter converting a count value of the counter to an analog voltage, and a comparator comparing the analog voltage outputted from the DA converter and the voltage induced in the capacitor, and the counter holds the count value when the analog voltage and the voltage induced in the capacitor become equal.

2. The level shift circuit of claim 1 , wherein the switching circuit comprises a first switch connected between the capacitor and the non-inversion input terminal of the differential amplification circuit, and a second switch connected between the holding circuit and the non-inversion input terminal of the differential amplification circuit.

3. The level shift circuit of claim 1 , wherein the input signal is a signal from an optical pickup.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033813 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 21, 2015
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034816/0510 →
CHANGE OF NAME Recorded Dec 3, 2014
From: SANYO SEMICONDUCTOR CO., LTD
To: SYSTEM SOLUTIONS CO., LTD.
Reel/Frame 034537/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033813/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2010
From: YOSHIMURA, TSUYOSHI; KAWAI, TAICHIRO
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.
Reel/Frame 024531/0657 →