Semiconductor device
View Patent ↗The invention prevents a source-drain breakdown voltage of a DMOS transistor from decreasing due to dielectric breakdown in a portion of a N type drift layer having high concentration formed in an active region near field oxide film corner portions surrounding an gate width end portion. The field oxide film corner portions are disposed on the outside of the gate width end portion so as to be further away from a P type body layer formed in the gate width end portion by forming the active region wider on the outside of the gate width end portion than in a gate width center portion. By this, the N type drift layer having high concentration near the field oxide film corner portions are disposed further away from the P type body layer without increasing the device area.
1. A semiconductor device comprising:
a semiconductor layer of a first general conductive type;
an element isolation insulation layer formed on the semiconductor layer and having an opening in plan view of the semiconductor layer, an inner edge of the opening in the element isolation insulation layer defining an active region in the plan view, and the active region being wider in a gate width end portion than in a gate width center portion in the plan view;
a body layer of a second general conductive type formed in the active region and comprising a channel region;
a source layer of the first general conductive type formed in the body layer;
a gate insulation film formed in the active region so as to cover the channel region;
a gate electrode formed on the gate insulating film;
a drift layer of the first general conductive type formed in the semiconductor layer; and
a drain layer of the first general conductive type formed in the drift layer,
wherein the inner edge of the opening in the element isolation insulation layer includes a corner portion in the plan view.
2. The semiconductor device of claim 1 , wherein the drift layer is disposed under the element isolation insulation layer so as to surround the body layer in the plan view, and the gate electrode extends outside the active region so as to be on the element isolation insulation layer.
3. The semiconductor device of claim 1 , wherein the gate insulation film is thicker in the gate width end portion and on an outside of the gate width end portion than in the gate center portion.
4. The semiconductor device of claim 1 , wherein the gate electrode surrounds the source layer in the plan view.
5. The semiconductor device of claim 4 , further comprising a gate electrode mounting insulation layer disposed in the active region between the gate width end portion and a lateral edge of the element isolation insulation layer in the plan view, a contact layer of the second general conductivity type formed between the source layer and the gate electrode mounting insulation layer, and an electron accumulation prevention layer of the second general conductive type disposed under the gate electrode mounting insulation layer, wherein the gate electrode extends so as to be on the gate electrode mounting insulation layer.
6. The semiconductor device of claim 1 , further comprising a contact layer of the second general conductivity type, wherein the contact layer is divided into at least two portions by the source layer in the plan view.