IP Library Granted Patent US 8,442,104
Granted Patent B2
US 8,442,104 · App. 12/788,561 · Granted May 14, 2013

Signal processing apparatus and signal processing method

Inventor: Kanji Takeda (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,442,104
App. No.
12/788,561
Granted
May 14, 2013
Kind
B2
Abstract

Provided is a signal processing apparatus including: an equalizer circuit that amplifies a predetermined frequency band of an input signal and outputs an output signal; a sampler circuit that samples the output signal amplified by the equalizer circuit with the output signal being offset in an amplitude direction using a multiphase clock system; an area information calculation circuit that calculates area information of an eye opening in an eye diagram of the output signal based on the output signal sampled by the sampler circuit; and a control circuit that controls amplification of the equalizer circuit based on the area information of the eye opening calculated by the area information calculation circuit.

Claims (22)

1. A signal processing apparatus comprising:

equalizer means that amplifies a predetermined frequency band of an input signal and outputs an output signal;

sampler means that samples the output signal amplified by the equalizer means with the output signal being offset in an amplitude direction using a multiphase clock system;

area information calculation means that calculates area information of an eye opening in an eye diagram of the output signal based on the output signal sampled by the sampler means; and

control means that controls amplification of the equalizer means stepwise based on the area information of the eye opening calculated by the area information calculation means so that the area of the eye opening calculated by the area information calculation means is maximized.

2. The signal processing apparatus according to claim 1 , wherein

the sampler means includes a plurality of flip-flop circuits that sample the output signal with the output signal being offset stepwise in the amplitude direction using the multiphase clock system, and

the area information calculation means includes:

a plurality of exclusive-OR circuits that perform an exclusive-OR operation based on output signals output from the plurality of flip-flop circuits; and

a counter circuit that counts the number of operation values output from the plurality of exclusive-OR circuits for each level of the offsetting, and calculates matrix information serving as the area information of the eye opening.

3. The signal processing apparatus according to claim 2 , wherein the counter circuit sets a first predetermined value to an element corresponding to the matrix information when the number of the operation values is equal to or greater than a threshold, and sets a second predetermined value to an element corresponding to the matrix information when the number of the operation values is less than the threshold.

4. The signal processing apparatus according to claim 3 , wherein

the counter circuit calculates the matrix information for each level of the amplification by the equalizer means, and

the control means controls the amplification of the equalizer means at a level where the number of the second predetermined values is maximum in the matrix information for each level of the amplification by the equalizer means.

5. The signal processing apparatus according to claim 1 , wherein the sampler means samples the output signal with the output signal being offset at seven levels in the amplitude direction using a six-phase clock system.

6. A signal processing method comprising:

amplifying a predetermined frequency band of an input signal and outputting an output signal;

sampling the amplified output signal with the output signal being offset in an amplitude direction using a multiphase clock system;

calculating area information of an eye opening in an eye diagram of the output signal based on the sampled output signal;

controlling the amplification based on the calculated area information of the eye opening;

sampling the amplified output signal with the output signal being offset stepwise in the amplitude direction using the multi-phase clock system; and

performing an exclusive-OR operation based on the sampled output signal, and counting the number of operation values obtained by the exclusive-OR operation for each level of the offsetting, to calculate matrix information serving as the area information of the eye opening.

Assignments (2)
CHANGE OF NAME Recorded Oct 26, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025191/0985 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2010
From: TAKEDA, KANJI
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024449/0690 →
Priority Claims (1)
JP 2009-128714 · May 28, 2009 · national
Continuity (1)
Related Publication 20100303143A1 · Dec 2, 2010