Driver with accurately controlled slew rate and limited current
View Patent ↗A driver circuit, that provides slew rate control of its output voltage, including a current generator, an output transistor, and optionally, a capacitor. The current generator has an input port, an output port and reference port. The output port couples to the gate of the output transistor. The capacitor couples between the gate and drain of the output transistor. The current generator controls a current I S flowing through the output port based on an input voltage at the input port. The current generator limits the absolute value of the current I S to be less than or equal to a maximum determined by a reference current Iref provided at the reference port. Modifications may be made to the driver circuit to limit the output current (e.g., as a function of the output voltage) and to make the slew rate limit independent of the gate-drain capacitance of the output transistor.
1. A driver circuit having a limited slew rate, the driver circuit comprising:
a current generator having an input port, an output port and reference port;
an output transistor, wherein the output port of the current generator is coupled to the gate of the output transistor;
wherein the current generator is configured to control a first current flowing through the output port based on an input voltage appearing at the input port, wherein the current generator is configured to limit the absolute value of the first current to be less than or equal to a maximum that is determined by a reference current provided at the reference port, wherein the current generator includes:
a transistor A;
a first chain of transistors; and
a second chain of transistors;
wherein the first chain and the second chain are coupled in parallel between a drive voltage and round, wherein a first transistor of the first chain is coupled to form a current mirror with a first transistor of the second chain, wherein the transistor A is configured to form a current mirror with a last transistor of the first chain, wherein the transistor A is also configured to form a current mirror with a last transistor of the second chain, wherein the reference current is provided to the drain of the transistor A, wherein the input port is coupled to the gates of second and third transistors in the second chain, wherein the second and third transistors of the second chain are coupled to a common node in drain-to-drain fashion, wherein the common node is coupled to the output port.
2. The driver circuit of claim 1 , wherein a drain of the output transistor is coupled to a supply voltage via a resistor.
3. A driver circuit having a limited slew rate, the driver circuit comprising:
a current generator having an input port, an output port and reference port;
an output transistor, wherein the output port of the current generator is coupled to the gate of the output transistor;
wherein the current generator is configured to control a first current flowing through the output port based on an input voltage appearing at the input port, wherein the current generator is configured to limit the absolute value of the first current to be less than or equal to a maximum that is determined by a reference current provided at the reference port, wherein the current generator includes:
first, second and third transistors, wherein a drain of the second transistor and a drain of the third transistor are connected to each other and to the output port of the current generator, wherein a source of the second transistor is coupled to a drive voltage node, wherein a source of the third transistor is coupled to ground;
a first pair of switches configured to turn off the third transistor and to enable a first connection when the input voltage is low, wherein, when the first connection is enabled, the second transistor is controlled by a fourth transistor in a first current mirror relationship;
a second pair of switches configured to turn off the second transistor and to enable a second connection when the input voltage is high, wherein, when the second connection is enabled, the third transistor is controlled by the first transistor in a second current mirror relationship.
4. The driver circuit of claim 3 , wherein the fourth transistor couples in series with a fifth transistor between the voltage drive node and wound, wherein the tifth transistor is controlled by the first transistor in a third current mirror relationship.
5. The driver circuit of claim 3 , wherein a drain of the output transistor is coupled to a supply voltage via a resistor.
6. A driver circuit having a limited slew rate, the driver circuit comprising:
a current generator having an input port, an input port and reference port;
an output transistor, wherein the output port of the current generator is coupled to the gate of the output transistor;
wherein the current generator is configured to control a first current flowing through the output port based on an input voltage appearing at the input port, wherein the current generator is configured to limit the absolute value of the first current to be less than or equal to a maximum that is determined by a reference current provided at the reference port
a transistor B coupled to a drive voltage node of the current generator, wherein a gate and a drain of the transistor B are shorted together, wherein the drive voltage node is driven with a known drive current, and
a transistor C whose gate is coupled to the drain of the output transistor, wherein the drain of the transistor C is coupled to the dr voltage node of the current generator, wherein the source of the transistor C is coupled to ground through a first resistor.
7. The driver circuit of claim 6 , wherein the transistor B is coupled to the drive voltage node through a second resistor.
8. A driver circuit having a limited slew rate, the driver circuit comprising:
a current generator having and input port, an output port and reference port;
an output transistor, wherein the output port of the current generator is coupled to the gate of the output transistor;
wherein the current generator is configured to control a first current flowing through the output port based on an input voltage appearing at the input port, wherein the current generator is configured to limit the absolute value of the first current to be less than or equal to a maximum that is determined by a reference current provided at the reference port;
a capacitor coupling between the output port of the current generator and a drain of the output transistor; and
wherein the output port of the current generator is coupled to the gate of the output transistor through an amplifier.
9. The driver circuit of claim 8 , wherein the amplifier includes a diamond follower circuit.
10. The driver circuit of claim 8 , wherein the amplifier includes an input stage and an output stage that are coupled together, where the input stage is coupled between a voltage node Vdd and ground, wherein a supply voltage node of the current generator is coupled to the voltage node Vdd, wherein the output stage is coupled between a voltage node Vdrive and ground.
11. The driver circuit of claim 10 further comprising a transistor B, wherein a gate and a drain of the transistor B are shorted together, wherein the drain of the transistor B couples to the voltage node Vdrive, wherein a source of the transistor couples to ground.
12. The driver circuit of claim 8 , wherein a drain of the output transistor is coupled to a supply voltage via a resistor.
13. A circuit comprising:
an input port, an output port, a drive port, and a reference port;
first, second, third, fourth, fifth, sixth and seventh and eighth transistors, wherein second and third transistors are coupled to a form a first series between a drive voltage rail and ground, wherein fourth, fifth, sixth and seventh transistors are coupled to form a second series between the drive voltage rail and ground, wherein the first and third transistors are coupled to form a first current mirror, wherein the first and seventh transistors are coupled to form a second current mirror, wherein the second and fourth transistors are coupled to form a third current mirror, and wherein the eighth transistor is diode-connected between the drive rail and ground;
wherein the input port is coupled to gates of the fifth and sixth transistors, wherein the output port is coupled to drains of the fifth and sixth transistors, wherein the reference port is coupled to the drain and gate of the first transistor, wherein the fifth and sixth transistors comprise one PMOS transistor and one NMOS transistor; and
wherein the drive port is coupled to the drive rail, and is configured to receive a known drive current that generates a voltage level on the drive rail.
14. The circuit of claim 13 , wherein the second and third transistors comprise one PMOS transistor and one NMOS transistor.
15. The circuit of claim 13 , wherein the reference port is supplied with a constant reference current.
16. The driver circuit of claim 13 , wherein the second, fourth and fifth transistors are PMOS transistors, wherein the first, third, sixth and seventh transistors are NMOS transistors.
17. A bridge driver device comprising:
Four driver circuits coupled in the H-bridge topology, wherein each of the four driver circuits includes:
a current generator having an input port, an output port and reference port;
an output transistor, wherein the output port of the current generator is coupled to the gate of the output transistor;
wherein the current generator is configured to control a first current flowing through the output port based on an input voltage appearing at the input port, wherein the current generator is configured to limit the absolute value of the first current to be less than or equal to a maximum that is determined by a reference current provided at the reference port;
wherein the output transistors of a first and second of the four driver circuits are PMOS transistors.
18. The bridge driver device of claim 17 , wherein each of the four driver circuits also includes a capacitor that couples between a gate of the corresponding output transistor and a drain of the corresponding output transistor.
19. The bridge driver device of claim 17 , further comprising a fan as a load device of the H-bridge topology.