SEMICONDUCTOR DEVICE AND ELECTROSTATIC DISCHARGE PROTECTION METHOD FOR THE SEMICONDUCTOR DEVICE

1 . A semiconductor device comprising an electrostatic discharge protection circuit, wherein the electrostatic discharge protection circuit comprises:

a power source system configured to supply a current to a semiconductor integrated circuit included in the semiconductor device through a power source potential line and a reference potential line;

a primary protection circuit configured to release a surge current to the power source system through a first node connected to a signal terminal when the surge current is generated at the signal terminal;

a trigger circuit configured to generate a trigger signal in response to a surge voltage generated at the power source system; and

a secondary protection circuit configured to release the surge current to the power source system through a second node connected between the first node and the semiconductor integrated circuit in response to the trigger signal.

2 . The semiconductor device according to claim 1 , further comprising:

a power source protection circuit configured to make conduction between the power supply potential line and the reference potential line in response to the trigger signal.

3 . The semiconductor device according to claim 1 , wherein the trigger circuit comprises:

a buffer circuit formed by at least one inverter element;

a first node configured to become high potential in response to the surge voltage being generated at the power source system; and

a second node configured to have a potential inverted to the first node by the first inverter element, and

the secondary protection circuit comprises a CMOS circuit,

a potential of the first node is supplied to a gate of an NMOS transistor included in the CMOS circuit, and

a potential of the second node is supplied to a gate of a PMOS transistor included in the CMOS circuit.

4 . A method for protecting a semiconductor device from an electrostatic discharge, wherein the semiconductor device comprises a power source system configured to supply a current to a semiconductor integrated circuit included in the semiconductor device through a power source potential line and a reference potential line, and

the method comprises:

releasing a surge current to the power source system through a first node connected to a signal terminal when the surge current is generated at the signal terminal;

generating a trigger signal in response to a surge voltage generated at the power source system; and

releasing the surge current to the power source system through a second node connected between the first node and the semiconductor integrated circuit in response to the trigger signal.

5 . The method for protecting a semiconductor device from the electrostatic discharge according to claim 4 , further comprising:

making conduction between the power supply potential line and the reference potential line in response to the trigger signal.

6 . The method for protecting a semiconductor device from the electrostatic discharge according to claim 4 , wherein a trigger circuit configured to generate the trigger signal comprises:

a buffer circuit formed by at least one inverter element;

a first node configured to become high potential in response to the surge voltage being generated at the power source system; and

a second node configured to have a potential inverted to the first node by the first inverter element, and

the releasing the surge current to the power source system through the second node is performed by a CMOS circuit composed of an NMOS transistor connected between a reference potential line and the second node and a PMOS transistor connected between the second node and the power source potential line, and

the releasing the surge current to the power source system through the second node comprises:

supplying a potential of the first node to a gate of the NMOS transistor; and

supplying a potential of the second node to a gate of the PMOS transistor.