IP Library Granted Patent US 8,359,427
Granted Patent B2
US 8,359,427 · App. 12/789,968 · Granted Jan 22, 2013

Semiconductor device

Inventor: Daisuke Sunaga (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,359,427
App. No.
12/789,968
Granted
Jan 22, 2013
Kind
B2
Abstract

In executing an EEPROM emulation by a flash memory incorporated in a semiconductor device, there is a problem that the data holding period of the flash memory is shorter than the EEPROM. The flash memory manages data by block unit. Therefore, it is required to securely perform a block change before the specification of the data holding period of the flash memory passes. For satisfying this problem, for an EEPROM substitution area in a flash memory, a data level check voltage is set between an internal verification voltage and a read-out voltage. When data level becomes below the data level check voltage, the block change is performed.

Claims (32)

1. A semiconductor device comprising:

a flash memory having an EEPROM substitution area for performing an EEPROM emulation;

a CPU; and

a data level check circuit configured to perform a comparison between a voltage level corresponding to a data written in any of blocks of the EEPROM substitution area and a predetermined data level check voltage;

wherein the CPU is configured to perform a block change by which the data is read out from said any of blocks and written in another block when the voltage level corresponding to the data becomes lower than the data level check voltage.

2. The semiconductor device according to claim 1 , further comprising:

a firmware which comprises a flash memory operation program performed by the CPU to perform writing and reading of the flash memory by block unit, and a data level check program performed by the CPU to control the data level check circuit,

wherein the flash memory further has:

a program area storing a predetermined user application being performed by the CPU; and

an EEPROM emulation library configured to perform an EEPROM emulation by calling the firmware by the CPU, and

the user application is configured to be performed by calling the flash memory operation program, and

the user application is configured to be performed by calling the block change at any timing independent from the flash memory operation program.

3. The semiconductor device according to claim 2 , wherein the flash memory operation program further comprises:

an erase program configured to erase said any of blocks after the data is read out from said any of blocks in the block change.

4. The semiconductor device according to claim 2 , wherein in the data level check program, the comparison is performed for all bits corresponding to data written in said any of blocks in the data level check program.

5. The semiconductor device according to claim 1 , wherein the flash memory further comprises:

a default data for overwriting the data when the voltage level corresponding to the data is out of a threshold voltage range in which the flash memory is set to be readable.

6. An emulation method of an EEPROM comprising:

performing a comparison between a voltage level corresponding to a data written in any of blocks of an EEPROM substitution area and a predetermined data level check voltage; and

performing a block change by which the data is read out from said any of blocks and written in other block when the voltage level corresponding to the data becomes lower than the data level check voltage.

7. The emulation method of the EEPROM according to claim 6 , further comprising:

performing a predetermined user application,

wherein the performing the predetermined user application comprises:

writing a data in any of blocks in the EEPROM substitution area;

reading the data written in said any of blocks from the EEPROM substitution area; and

performing the comparison at any timing independent from the writing and the writing.

8. The emulation method of the EEPROM according to claim 6 , wherein the performing the block change comprises:

erasing said any of blocks after the data is read out from said any of blocks.

9. The emulation method of the EEPROM according to claim 6 , wherein the performing the comparison comprises:

performing the comparison for all bits corresponding to data written in said any of blocks.

10. The emulation method of the EEPROM according to claim 6 , wherein the performing the block change comprises:

overwriting the data to a default data when the voltage level corresponding to the data is out of a threshold voltage range in which the flash memory is set to be readable.

Assignments (2)
CHANGE OF NAME Recorded Oct 26, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025191/0985 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2010
From: SUNAGA, DAISUKE
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024477/0991 →
Priority Claims (1)
JP 2009-144500 · Jun 17, 2009 · national
Continuity (1)
Related Publication 20100325350A1 · Dec 23, 2010