Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer
A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic.
1. A method for generating a core timing model of a core logic through a computing system, the method comprising:
determining a location of un-wired tracks in an outermost layer of the core logic after a core logic routing;
metal filling the un-wired tracks after the core logic routing;
constructing an adjacent layer that is adjacent to the outermost layer of the core logic, the constructing of the adjacent layer including orienting a grounded metal in the adjacent layer in an orientation that is orthogonal to a direction of the un-wired tracks; and
generating at least one of a delay model and a cross-talk immune model of a hierarchical arrangement independent of any logic type through said computing system.
2. The method of claim 1 , wherein the metal filling of the un-wired tracks includes filling the un-wired tracks with a metal including substantially similar physical characteristics to the grounded metal.
3. The method of claim 1 , wherein the constructing of the adjacent layer includes constructing the adjacent layer including a core window that approximately occupies an area of the core logic, wherein the grounded metal resides in the core window.
4. The method of claim 1 , wherein the constructing of the adjacent layer includes constructing the adjacent layer including a chip-level routing layer having a set of routes configured to provide chip-level routing.
5. The method of claim 4 , wherein the set of routes of the chip-level routing layer is configured to provide at least one of chip-level signal routes, clock routes, and power routes.
6. The method of claim 4 , wherein the grounded metal in the chip-level routing layer represents a similar parasitic characteristic of the core logic during generation of the core timing model.
7. The method of claim 1 , further comprising:
generating the core timing model based on a parasitic capacitance due to an interaction between the outermost layer of the core logic and the adjacent layer.
8. The method of claim 7 , further comprising:
removing the adjacent layer after the core timing model of the core logic has been generated.
9. The method of claim 1 , wherein the generating of the core timing model includes utilizing a static timing analysis tool.
10. The method of claim 1 , including utilizing the core timing model to decrease a minimum delay value of a delay model prediction range by 5% and to increase a maximum delay value of the delay model prediction range by 2% to account for grounding gaps and other non-idealities.
11. An integrated circuit representation on a computer system comprising:
a microchip substrate;
a core logic layer including an outermost core logic layer having a set of un-wired tracks that are metal filled based on determining a location of the set of un-wired tracks; and
a chip-level routing layer adjacent to the outermost chip-level routing layer, the chip-level routing layer including another set of un-wired tracks that are metal filled, and the chip-level routing layer being constructed through orienting a grounded metal in an orientation that is orthogonal to a direction of the un-wired tracks,
wherein at least one of a delay model and a cross-talk immune model of a hierarchical arrangement of a high-level representation of the integrated chip is configured to be generated through the computing system independent of any logic type.
12. The integrated circuit representation of claim 11 , wherein a first metal filling of the set of un-wired tracks is typical for the core logic layer and a second metal filling of the other set of un-wired tracks is typical for the chip-level routing layer.
13. The integrated circuit representation of claim 12 , wherein the first metal filling of the set of un-wired tracks and the second metal filling of the other set of un-wired tracks include a same metal.
14. The integrated circuit representation of claim 12 , wherein the chip-level routing layer includes a core window, and wherein the second metal filling of the chip-level routing layer resides in the core window.
15. The integrated circuit representation of claim 14 , wherein the core window of the chip-level routing layer spatially occupies, at least substantially, an area of the core logic.
16. The integrated circuit representation of claim 11 , wherein a core timing model for the core logic layer that is generated through the computing system based on the metal filled set of un-wired tracks of the core logic layer, and the metal filled other set of un-wired tracks of the chip-level routing layer, represents an over-core routing in the chip-level routing layer.
17. The integrated circuit representation of claim 16 , wherein the core timing model is configured to be used in over-core routing of a plurality of different chip-level arrangements.
18. The integrated circuit representation of claim 11 , wherein the chip-level routing layer includes a set of routes configured to provide at least one of signal routes, clock routes and power routes.