MICROCOMPUTER AND MICROCOMPUTER SYSTEM

1 . A microcomputer comprising:

a CPU;

a standby controller that controls setting of and recovering from sleep mode of said CPU;

an output terminal;

a first timer;

an output terminal controller that, when said first timer performs predetermined time measurement when said CPU is in said sleep mode, changes level of said output terminal while maintaining said sleep mode; and

a second timer that starts time measurement when said output terminal controller changes the level of said output terminal in said sleep mode; wherein

said standby controller performs recovering from said sleep mode of said CPU when said second timer performs a prescribed time measurement.

2 . The microcomputer according to claim 1 , further comprising:

a main clock controller that supplies a main clock to said CPU when said CPU is in an operating state, and stops said main clock when set to said sleep mode; and

a subclock controller that supplies a subclock to said first timer and said second timer.

3 . The microcomputer according to claim 1 , wherein,

in said sleep mode, said CPU temporarily stops operation while holding internal data, and when recovering from said sleep mode is performed, by said standby controller, operation is restarted from said temporarily stopped state.

4 . The microcomputer according to claim 2 , wherein

each of said first and second timers comprises:

a counter that counts said subclock;

a compare register that can be set to an arbitrary value by an instruction of said CPU; and

a comparison unit that outputs a match detection signal when values of said counter and said compare register match.

5 . The microcomputer according to claim 4 , wherein a value that is independent of said compare register of said first timer can be set in said compare register of said second timer.

6 . The microcomputer according to claim 4 , wherein

when a match detection signal of said first timer is received when in said sleep mode,

said output terminal controller changes output voltage level of said output terminal, and

said second timer starts a count by said counter.

7 . The microcomputer according to claim 4 , wherein, in said sleep mode, said standby controller receives a match detection signal of said second timer and performs recovering from said sleep mode.

8 . A microcomputer system comprising a microcomputer and an external device controlled by said microcomputer, said microcomputer and said external device each having a normal operation mode and a sleep mode with lower power consumption than said normal operation mode, wherein

said microcomputer comprises:

an output terminal that controls said modes of said external device;

a first timer that, when both of said microcomputer and said external device are in said sleep mode, measures time to wake up said external device;

an output terminal controller that, when said first timer has measured said wake-up time of said external device, changes level of said output terminal and wakes up said external device, while maintaining said sleep mode of said microcomputer; and

a second timer that, when said first timer measures time for wake-up of said external device, starts a count, measures wake-up time of said microcomputer, and when said wake-up time of said microcomputer has come, performs recovering said microcomputer from said sleep mode to return to said normal operation mode.

9 . The microcomputer system according to claim 8 , wherein said second timer measures time for recovering from sleep mode of said microcomputer so that said microcomputer and said external device enter normal operation mode substantially at the same time.

10 . The microcomputer system according to claim 8 , wherein measurement times of said first and second timers are configured so that each can be set independently.

11 . The microcomputer system according to claim 8 , wherein said microcomputer and said external device are formed on the same semiconductor substrate.