Semiconductor device

1. A semiconductor device, comprising:

normal lines arranged for transfer of signals;

a shield line arranged adjacent to the normal lines;

a level shifting circuit for receiving an input signal swinging between a power supply voltage and a ground voltage, and shifting the input signal to level-shifted signal swinging between a high voltage, higher than the power supply voltage by a predetermined level, and the ground voltage so that a logic state of an output signal output to an output node is maintained regardless of variations of the signals of the normal lines; and

a signal input unit in response to the level-shifted signal provided via the shield line to selectively couple the output node to the ground voltage, wherein the signal input unit comprises a pull-up circuit for receiving the level-shifted signal and the predetermined level is equal to or greater than a threshold voltage of the pull-up circuit.

2. The semiconductor device as recited in claim 1 , wherein the level shifting circuit includes:

a high level shifter for level-shifting a level of the input signal to swing between the high voltage and the ground voltage; and

a driver for driving the shield line by using the signal level-shifted by the high level shifter.

3. The semiconductor device as recited in claim 2 , wherein the high level shifter includes:

a first NMOS transistor having one side connected to the ground voltage supplying terminal and a gate coupled to the input signal;

an inverter receiving the input signal via an input terminal;

a second NMOS transistor having one side connected to a ground voltage supplying terminal and a gate coupled to an output of the inverter;

a first PMOS transistor having one side connected to the second side of the first NMOS transistor, a gate connected to the second side of the second NMOS transistor, and a second side connected to a high voltage supplying terminal through which the high voltage is supplied; and

a second PMOS transistor having one side connected to the second side of the second NMOS transistor, a gate connected to the second side of the first NMOS transistor, and a second side connected to the high voltage supplying terminal.

4. The semiconductor device as recited in claim 3 , wherein the driver includes:

a third PMOS transistor having one side connected to the high voltage supplying terminal and a gate coupled to an output of the level shifter; and

a third NMOS transistor having one side connected to the other side of the third PMOS transistor, a gate coupled to an output of the level shifter, and a second side connected to the ground voltage supplying terminal.

5. The semiconductor device as recited in claim 1 , wherein the pull-up circuit is provided with a MOS transistor having one side connected to the output node, a gate connected to the shield line, and a second side connected to the power supply voltage supplying terminal.

6. The semiconductor device as recited in claim 5 , wherein the high voltage is higher than the power supply voltage by a level above a threshold voltage of the MOS transistor.

7. The semiconductor device as recited in claim 1 , wherein the normal lines are disposed in a region adjacent to one side of the shield line and a region adjacent to the other side of the shield line, respectively.

8. The semiconductor device as recited in claim 1 wherein the shield line is a line in which a predetermined voltage level is set during an initial operation of the semiconductor device and the voltage level is not varied during a normal operation.

9. The semiconductor device as recited in claim 1 , wherein the input signal transferred through the shield line is at least one of a signal for controlling a burst length of a semiconductor device, a signal for controlling a CAS latency, a control signal for controlling on/off operations of a delay locked loop, a control signal for controlling ODT, a control signal for deciding a driving capability of the output driver, a control signal for controlling a timing of write recovery, and a control signal for controlling a test mode.

10. A method for driving a semiconductor device, comprising the steps of:

receiving an input signal swinging between a power supply voltage and a ground voltage;

shifting the input signal to a level-shifted signal swinging between a high voltage, higher than the power supply voltage by a predetermined level, and the ground voltage so that a logic state of an output signal output to an output node is maintained regardless of variations of signals of the normal lines; and

in response to the level-shifted signal provided via the shield line, selectively coupling the output node to the ground voltage by using a pull-up circuit to receive the level-shifted signal, wherein the predetermined level is equal to or greater than a threshold voltage of the pull-up circuit.

11. The method as recited in claim 10 , wherein the shifting step includes the steps of:

shifting a signal level of the input signal to the high voltage; and

driving the shield line by using the level-shifted signal.

12. The method as recited in claim 11 , wherein the high voltage is higher than the power supply voltage by a level above a threshold voltage of a MOS transistor.

13. The method as recited in claim 10 , wherein the shield line is a line in which a predetermined voltage level is set during an initial operation of the semiconductor device and the voltage level is not varied during a normal operation.

14. The method as recited in claim 10 , wherein the input signal transferred through the shield line is at least one of a signal for controlling a burst length of a semiconductor device, a signal for controlling a CAS latency, a control signal for controlling on/off operations of a delay locked loop, a control signal for controlling ODT, a control signal for deciding a driving capability of the output driver, a control signal for controlling a timing of write recovery, and a control signal for controlling a test mode.