Semiconductor device
A semiconductor device according to an exemplary embodiment of the present invention includes a memory cell including an information storage portion including a capacitor upper electrode of a DRAM cell and a capacitor lower electrode formed below the upper electrode and an access transistor for controlling access to the information storage portion, a bit-line connected to the access transistor to write or read data to or from the information storage portion, a word line connected to a gate electrode of the access transistor to control the access transistor, and a capacitive element including an upper electrode made from a same layer as a first metal line formed above the capacitor upper electrode and a lower electrode made from a same layer as the capacitor upper electrode, the capacitive element being formed outside an area where the memory cell is formed.
1 . A semiconductor device comprising:
a memory cell including an information storage portion including an upper electrode layer and a lower electrode layer formed below the upper electrode layer and an access transistor for controlling access to the information storage portion;
a bit-line connected to the access transistor to write or read data to or from the information storage portion;
a word line connected to a gate electrode of the access transistor to control the access transistor; and
a first capacitive element including a first metal line formed above the upper electrode layer and an electrode layer made from a same layer as the upper electrode, the first capacitive element being formed outside an area where the memory cell is formed.
2 . The semiconductor device according to claim 1 , wherein the electrode layer that is made from the same layer as the upper electrode and serves as a lower electrode layer of the first capacitive element is formed in a process carried out after formation of the electrode layer of the bit-line.
3 . The semiconductor device according to claim 1 , further comprising a transistor formed below the first capacitive element, the transistor including a diffusion layer connected to a wiring layer made from a same layer as a wiring layer of the bit-line, the diffusion layer being used as a source or a drain of the transistor.
4 . The semiconductor device according to claim 1 , further comprising a second capacitive element formed below the first capacitive element, the second capacitive including a diffusion layer connected to a wiring layer made from a same layer as a wiring layer of the bit line and an electrode layer made from a same layer as a gate electrode of the access transistor.
5 . The semiconductor device according to claim 4 , wherein a voltage applied between electrodes of the first capacitive element differs from a voltage applied to the second capacitive element.
6 . The semiconductor device according to claim 1 , wherein the memory cell is one of a DRAM cell, a FeRAM cell and a phase-change memory.