Granted Patent B2

US 8,320,155 · App. 12/801,539 · Granted Nov 27, 2012

Abstract

Claims (32)

1. A semiconductor integrated circuit device comprising a memory array comprising:

mats each comprising memory cells each having two transistors and one storage element connected in series in this order between a corresponding one of bit lines and a constant voltage, said two transistors respectively having gate electrodes respectively connected to a corresponding one of first word lines orthogonal to said bit lines and a corresponding one of second word lines parallel to said bit lines, and said memory cells disposed at all intersections between said bit lines and said first word lines;

sense amplifiers each input with a corresponding pair of the bit lines in the same mat as a bit line pair;

first word drivers adapted to activate said first word lines, respectively; and

second word drivers adapted to activate said second word lines, respectively.

2. The semiconductor integrated circuit device according to claim 1 , wherein said two transistors comprise surround gate transistors stacked in two tiers at a same planar position and the memory cell is selected by simultaneously activating the corresponding first and second word lines.

3. The semiconductor integrated circuit device according to claim 1 , wherein said storage element comprises a capacitor and wherein said capacitor comprises a stack capacitor formed above a semiconductor substrate and said bit lines are formed buried in said semiconductor substrate.

4. The semiconductor integrated circuit device according to claim 1 , wherein said storage element comprises a capacitor and wherein said capacitor comprises a trench capacitor formed buried in a semiconductor substrate and said bit lines are formed above said semiconductor substrate.

5. The semiconductor integrated circuit device according to claim 1 , wherein said first word lines are orthogonal to said bit lines, said second word lines are parallel to said bit lines, and said first and second word lines are orthogonal to each other and wherein, by simultaneously selecting and activating the corresponding first and second word lines, the memory cell at the intersection therebetween is selected.

6. The semiconductor integrated circuit device according to claim 1 , wherein each of said sense amplifiers is shared by the corresponding bit line pairs disposed in adjacent mats.

7. The semiconductor integrated circuit device according to claim 6 , wherein said each of said sense amplifiers is shared by the corresponding bit line pairs disposed in each of said adjacent mats.

8. The semiconductor integrated circuit device according to claim 1 , wherein each of said second word drivers is shared between adjacent mats.

9. A method for accessing a semiconductor integrated circuit device comprising a memory array comprising mats each comprising memory cells each having two transistors and one storage element connected in series in this order between a corresponding one of bit lines and a constant voltage, said two transistors respectively having gate electrodes respectively connected to a corresponding one of first word lines orthogonal to said bit lines and a corresponding one of second word lines parallel to said bit lines, and said memory cells disposed at all intersections between said bit lines and said first word lines, sense amplifiers each input with a corresponding pair of the bit lines in the same mat as a bit line pair, first word drivers adapted to activate said first word lines, respectively, and second word drivers adapted to activate said second word lines, respectively, said method comprising:

accessing a first memory cell by selecting the corresponding first and second word lines;

then accessing a second memory cell by non-selecting said second word line;

precharging and equalizing the bit lines; and

selecting the second word line at a different address.

10. The semiconductor integrated circuit device according to claim 1 , wherein each said mat has its own said second word driver.

11. The memory array according to claim 10 , wherein each said mat has its own said second word driver.

12. A semiconductor integrated circuit device comprising:

a bit line;

a first word line;

a second word line; and

a first transistor, a second transistor and a storage element coupled in series between the bit line and a terminal supplying a specific voltage to form a memory cell, a gate of the first transistor coupled to the first word line, and a gate of the second transistor coupled to the second word line.

13. The device according to claim 12 , wherein each of said first and second transistors comprises a surround gate transistor.

14. The device according to claim 12 , further comprising a first word driver coupled to the first word line to drive the first word line, and a second word driver coupled to the second word line to drive the second line.

15. The device according to claim 14 , wherein the first and second word driver respectively drive the first and second word line when a data stored in the storage is read out to the bit line and a data on the bit line is stored to the storage.

16. The device according to claim 12 , wherein the first word line is elongated to a first direction and the bit line is elongated to a second direction different from the first direction.

17. The device according to claim 12 , wherein the first word line is elongated to a first direction and the second word line is elongated to a second direction different from the first direction.

18. The device according to claim 12 , wherein the first transistor, the second transistor and the storage element are vertically arranged.

19. The device according to claim 12 , wherein the storage element is a capacitor.

20. The device according to claim 14 , wherein the first word driver drives the first word line in a first period and the second word driver drives the second word line in a second period different from the first period.

Assignments (8)