Nitride semiconductor substrate, production method therefor and nitride semiconductor device

1. A nitride semiconductor substrate, comprising:

two principal surfaces comprising an upper surface that is a growth face and a lower surface on its opposite side,

wherein a full width at half maximum (FWHM) in a surface layer of the substrate at depths of from 0 to 250 nm from the upper surface is narrower than an FWHM in an inner layer of the substrate at depths exceeding 5 μm from the upper surface, where the FWHMs are obtained by X-ray rocking curve measurement using diffraction off a particular asymmetric plane of the substrate inclined relative to the upper surface, and

wherein the FWHM in the surface layer of the substrate is not more than 90% of the FWHM in the inner layer of the substrate.

2. The nitride semiconductor substrate according to claim 1 , wherein the substrate comprises a GaN freestanding substrate, an AlN freestanding substrate, or an Al x Ga 1-x N freestanding substrate (0≦x≦1).

3. The nitride semiconductor substrate according to claim 1 , wherein the asymmetric plane is chosen so as to satisfy a specific condition shown below:

when an apex of a virtual cone, whose axis is normal to the asymmetric plane and an apex angle of (180-2θ) degrees wherein θ is a Bragg angle of the asymmetric plane, is put on a sample surface, the virtual cone and the sample surface intersect each other.

4. The nitride semiconductor substrate according to claim 3 , wherein the upper surface comprises a {0001} plane or a plane slightly inclined at not more than 10 degrees thereto, while the asymmetric plane comprises a {10-11}, {10-12}, {10-13}, {20-21}, or {11-22} plane.

5. The nitride semiconductor substrate according to claim 3 , wherein the upper surface comprises a {10-10} plane or a plane slightly inclined at not more than 10 degrees thereto, while the asymmetric plane comprises a {10-11}, {10-12}, {10-13}, {10-14}, {10-15}, {10-16}, {11-20}, or {11-22} plane.

6. The nitride semiconductor substrate according to claim 3 , wherein the upper surface comprises a {11-20} plane or a plane slightly inclined at not more than 10 degrees thereto, while the asymmetric plane comprises a {10-10} or {11-22} plane.

7. The nitride semiconductor substrate according to claim 3 , wherein the upper surface comprises a {11-22} plane or a plane slightly inclined at not more than 10 degrees thereto, while the asymmetric plane comprises a {0001} or {11-20} plane.

8. The nitride semiconductor substrate according to claim 3 , wherein the upper surface comprises a {10-11} plane or a plane slightly inclined relative thereto, while the asymmetric plane comprises a {0001} or {10-10} plane.

9. The nitride semiconductor substrate according to claim 3 , wherein the upper surface comprises a {10-12} plane or a plane slightly inclined relative thereto, while the asymmetric plane comprises a {0001}, {10-10}, or {10-11} plane.

10. The nitride semiconductor substrate according to claim 3 , wherein the upper surface comprises a {20-21} plane or a plane slightly inclined relative thereto, while the asymmetric plane comprises a {0001}, {10-12}, {10-13}, {10-14}, or {10-15} plane.

11. A nitride semiconductor device, comprising:

the nitride semiconductor substrate according to claim 1 ; and

an epitaxial layer comprising a nitride semiconductor substrate crystal formed over the nitride semiconductor substrate.

12. A method for producing a nitride semiconductor substrate, said nitride semiconductor substrate comprising:

two principal surfaces comprising an upper surface that is a growth face and a lower surface on its opposite side,

wherein an FWHM (full width at half maximum) in a surface layer of the substrate at depths of from 0 to 250 nm from the upper surface is narrower than an FWHM in an inner layer of the substrate at depths exceeding 5 μm from the upper surface, where the FWHMs are obtained by X-ray rocking curve measurement using diffraction off a particular asymmetric plane of the substrate inclined relative to the upper surface,

said method comprising:

mechanically polishing or surface grinding a surface of a single crystal to form a principal surface so that a root mean square (RMS) is not more than 5 nm;

subsequently chemically mechanically polishing (CMP) with colloidal silica or dry etching the surface to reduce damage caused by the mechanical polishing or the surface grinding so that the RMS is not more than 2 nm; and

subsequently dripping onto the surface a not more than 2 mol % ammonium fluoride containing solution with not more than 100 nm particle diameter gallium oxide nanopowder added thereto, and irradiating the surface with ultraviolet rays over 1 hour, to apply friction to the surface.