Register selection circuitry receiving select signals from test interfaces
A TAP linking module ( 21, 51 ) permits plural TAPs (TAPs 1 - 4 ) to be controlled and accessed from a test bus ( 13 ) via a single TAP interface ( 20 ).
1. An integrated circuit, comprising:
A. a test bus of signals that include a test data in lead, a test data out lead, a test clock lead, and a test mode select lead;
B. target circuits;
C. test interfaces, each test interface includes a state machine coupled with an instruction register and a data register, the data register being connected with one of the target circuits, each test interface is coupled to the test bus and is connected to one of the target circuits, and each test interface has a select output;
D. a shift register separate from the test interfaces; and
E. selection circuitry connected to the select outputs and coupled with the shift register to selectively couple the shift register with the test bus.
2. The integrated circuit of claim 1 in which each test interface is connected to the test data in lead, the test clock lead, and the test mode select lead, and is selectively coupled to the test data output.
3. The integrated circuit of claim 1 including a test access port linking module that includes the shift register and selection circuitry, the linking module including a separate enable output connected to each test interface.
4. The integrated circuit of claim 1 in which the shift register is a two bit register.
5. The integrated circuit of claim 1 including a state machine separate from the test interfaces and coupled with the test bus, the shift register, and the selection circuitry.
6. The integrated circuit of claim 1 including a first test access port controller including a state machine and having control outputs coupled to the shift register, and in which each of the test interfaces include a test access port controller including a state machine, the test access port controllers of the test interfaces being separate from the first test access port controller.
7. The integrated circuit of claim 1 in which the shift register includes a serial input connected to the test data in lead.
8. The integrated circuit of claim 1 including a first test access port controller including a state machine and having control outputs coupled to the shift register and in which each of the test interfaces include a test access port controller including a state machine, the test access port controllers of the test interfaces being separate from the first test access port controller, the first test access port controller being connected to the selection circuitry.