Gate pattern of semiconductor device and method for fabricating the same

1. A method for fabricating a semiconductor device, comprising:

forming a recess pattern by selectively etching a substrate;

forming a gate dielectric layer by filling the recess pattern on the substrate;

forming a groove by selectively etching the gate dielectric layer, wherein a bottom surface of the groove is higher than the highest surface of the substrate;

forming a polysilicon electrode filling the groove;

forming an electrode metal layer on the polysilicon electrode and the gate dielectric layer; and

forming a gate pattern by etching the electrode metal layer and the gate dielectric layer,

wherein the recess pattern is formed along an edge portion of the gate pattern as a quadrilateral periphery,

wherein the gate dielectric layer below the edge portion of the gate pattern has a lower protruding area completely filling the recess pattern both in the length direction and the width direction of a channel.

2. The method of claim 1 , wherein the lower protruding area is formed as the quadrilateral periphery.

3. The method of claim 1 , wherein the gate dielectric layer comprises an oxide layer and an oxynitride layer stacked on each other.

4. The method of claim 3 , wherein the oxynitride layer is formed by nitrating the oxide layer to a certain thickness.

5. The method of claim 1 , wherein the electrode metal layer is formed of tungsten.

6. The method of claim 1 , further comprising forming a gate spacer of a nitride layer to cover both sidewalls of the gate pattern.

7. The method of claim 1 , wherein the gate dielectric layer surrounds the polysilicon electrode both in the length direction and the width direction of the channel.

8. The method of claim 1 , wherein an edge portion of the channel is surrounded by the gate dielectric layer.

9. A gate pattern of a semiconductor device, comprising:

a substrate having a recess pattern;

a gate dielectric layer formed on the substrate, filling the recess pattern and protruding over the substrate, and having a groove, wherein a bottom surface of the groove is higher than the highest surface of the substrate;

a polysilicon electrode filling the groove; and

a metal electrode formed on the polysilicon electrode and the gate dielectric layer,

wherein the gate dielectric layer below an edge portion of the gate pattern has a lower protruding area completely filling the recess pattern both in the length direction and the width direction of a channel.

10. The gate pattern of claim 9 , wherein the recess pattern is formed along an edge portion of the gate pattern as a quadrilateral periphery.

11. The gate pattern of claim 9 , wherein the lower protruding area is formed as a quadrilateral periphery.

12. The gate pattern of claim 9 , wherein the gate dielectric layer comprises an oxide layer and an oxynitride layer stacked on each other.

13. The gate pattern of claim 9 , further comprising:

a gate hard mask formed on the metal electrode; and

a gate spacer formed on sidewalls of the gate hard mask, the metal electrode, and the gate dielectric layer.

14. The gate pattern of claim 9 , further comprising

a gate spacer of a nitride layer formed on the gate pattern to cover both sidewalls of the gate pattern.

15. The gate pattern of claim 10 , wherein the gate dielectric layer surrounds the polysilicon electrode both in the length direction and the width direction of the channel.

16. The gate pattern of claim 15 , wherein an edge portion of the channel is surrounded by the gate dielectric layer.