IP Library Granted Patent US 8,410,803
Granted Patent B2
US 8,410,803 · App. 12/820,623 · Granted Apr 2, 2013

Test apparatus of semiconductor device and method thereof

Inventors: Nobuhiro Sawa (Ohtsu, JP); Kouichi Minami (Ohtsu, JP); Masato Chiba (Kuroishi, JP)
Assignees: Renesas Electronics Corporation; Kabushiki Kaisha Nihon Micronics
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Quick Facts
Patent No.
US 8,410,803
App. No.
12/820,623
Granted
Apr 2, 2013
Kind
B2
Abstract

A test apparatus according to the present invention includes a probe card recognition unit that recognizes positions of at least two probe card marks formed to a probe card and assumes a probe card mark connection line connecting the positions of the probe card marks, a backing material recognition unit that recognizes positions of at least two backing material marks formed to a backing material where a semiconductor chip is fixed thereto and assumes a backing material mark connection line connecting the positions of the backing material mark, a positional relationship recognition unit that recognizes a positional relationship between the probe card and the backing material according to the probe card mark connection line and the backing material mark connection line, and a correction unit that corrects the position of at least one of the probe card and the backing material according to the positional relationship.

Claims (22)

1. A test apparatus of a semiconductor device comprising:

a probe card recognition unit that recognizes positions of at least two probe card marks on a probe card, and the probe card recognition unit recognizes an imaginary probe card mark connection line formed by connecting the positions of the at least two probe card marks;

a backing material recognition unit that recognizes positions of at least two backing material marks on a backing material mark, and the backing material recognition unit recognizes an imaginary backing material mark connection line formed by connecting the positions of the at least two backing material marks;

a positional relationship recognition unit that recognizes a positional relationship between the probe card and the backing material according to the probe card mark connection line and the backing material mark connection line; and

a correction unit that corrects the position of at least one of the probe card and the backing material according to the positional relationship.

2. The test apparatus of the semiconductor device according to claim 1 , wherein the probe card mark is formed to a body part that fixes a plurality of probes to a substrate part.

3. The test apparatus of a semiconductor device according to claim 2 , wherein

the body part comprises:

a frame that at least one opening is formed; and

at least two projected parts, the projected parts being formed integrally with the frame and placed in the opening, and

the probe card mark is formed to the projected part.

4. The test apparatus according to claim 1 , wherein the backing material marks are at least two electrode pads used at the time of a test process.

5. The test apparatus according to claim 1 , wherein the backing marks are alignment marks formed to a place where a conductor pattern of the backing material is not formed.

6. The test apparatus according to claim 1 , further comprising a display unit that displays a first line and a second line in order to enable visual comparison between the first and the second lines, the first line corresponding to the probe card mark connection line and indicating an orientation of the probe card, and the second line corresponding to the backing material mark connection line and indicating an orientation of the backing material.

7. A method of testing a semiconductor device comprising:

recognizing positions of at least two probe card marks on a probe card using a probe card recognition device;

recognizing an imaginary probe card mark connection line formed by connecting the positions of the at least two probe card marks using the probe card recognition device;

recognizing positions of at least two backing material marks on a backing material mark using a backing material recognition device;

recognizing an imaginary backing material mark connection line formed by connecting the positions of the at least two backing material marks using the backing material recognition device;

recognizing a positional relationship between the probe card and the backing material according to the probe card mark connection line and the backing material mark connection line using a positional relationship recognition device; and

correcting the position of at least one of the probe card and the backing material according to the positional relationship using a correction device.

8. The method according to claim 7 , further comprising displaying a first line and a second line in order to enable visual comparison between the first and the second lines, the first line corresponding to the probe card mark connection line and indicating an orientation of the probe card, and the second line corresponding to the backing material mark connection line and indicating an orientation of the backing material.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Oct 26, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025191/0916 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2010
From: SAWA, NOBUHIRO; MINAMI, KOUICHI; CHIBA, MASATO
To: NEC ELECTRONICS CORPORATION; KABUSHIKI KAISHA NIHON MICRONICS
Reel/Frame 024574/0947 →
Priority Claims (1)
JP 2009-171823 · Jul 23, 2009 · national
Continuity (1)
Related Publication 20110018569A1 · Jan 27, 2011