IP Library Granted Patent US 7,867,856
Granted Patent B2
US 7,867,856 · App. 12/822,862 · Granted Jan 11, 2011

Method of manufacturing a semiconductor device having fin-field effect transistor

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Quick Facts
Patent No.
US 7,867,856
App. No.
12/822,862
Granted
Jan 11, 2011
Kind
B2
Abstract

A semiconductor device includes an element isolation region formed in a semiconductor substrate, an active region surrounded by the element isolation region, and a gate electrode formed in one direction to cross the active region. The semiconductor substrate includes two gate trenches formed in parallel to a major axis direction of the active region in the active region, and a fin-shaped part which is located between the two gate trenches. The gate electrode is buried in the two gate trenches and formed on the fin-shaped part. The fin-shaped part serves as a channel region. A fin field effect transistor in which a width of the channel region is smaller than a gate length is thereby obtained.

Claims (24)

1. A method of manufacturing a semiconductor substrate comprising steps of:

forming a mask layer on a semiconductor substrate, the mask layer covering up a region to serve as an active region and including an opening for exposing a region to serve as an STI region;

forming a trench for the STI region using the mask layer;

forming a first insulating film in the trench and in the opening of the mask layer without removing the mask layer;

forming a second opening corresponding to the mask layer in the first insulating film by selectively removing the mask layer;

forming a sidewall insulating film on an inner wall of the second opening;

forming a second insulating film in the second opening in which the sidewall insulating film is formed;

selectively removing the sidewall insulating film in a region in which a gate electrode is to be formed;

forming two trenches in the region in which the gate electrode is to be formed on the semiconductor substrate using the first insulating film and the second insulating film as a mask, and forming a fin-shaped part which is located between the two gate trenches, which is a part of the semiconductor substrate, and which is to serve as a channel region;

forming a gate insulating film at least on an upper surface and a side surface of the fin-shaped part; and

forming the gate electrode buried in the two gate trenches and covering up the fin-shaped part.

2. The method of manufacturing the semiconductor device as claimed in claim 1 , wherein a width of the channel region is smaller than a gate length.

3. The method of manufacturing the semiconductor device as claimed in claim 1 , further comprising:

forming a source region and a drain region by implanting impurity ions into the semiconductor substrate using the gate electrode as a mask; and

selectively removing the gate insulating film formed on surfaces of the source region and the drain region, thereby forming contact regions on the surfaces of the source region and the drain region, respectively.

4. The method of manufacturing the semiconductor device as claimed in claim 2 , further comprising:

forming a source region and a drain region by implanting impurity ions into the semiconductor substrate using the gate electrode as a mask; and

selectively removing the gate insulating film formed on surfaces of the source region and the drain region, thereby forming contact regions on the surfaces of the source region and the drain region, respectively.

5. The method of manufacturing the semiconductor device as claimed in claim 3 , wherein a width of the contact region in one direction to cross the active region is larger than a width of the channel region.

6. The method of manufacturing the semiconductor device as claimed in claim 4 , wherein a width of the contact region in one direction to cross the active region is larger than a width of the channel region.

7. The method of manufacturing the semiconductor device as claimed in claim 1 , wherein the gate insulating film is formed on both side surfaces of the fin-shaped part.

8. The method of manufacturing the semiconductor device as claimed in claim 2 , wherein the gate insulating film is formed on both side surfaces of the fin-shaped part.

9. The method of manufacturing the semiconductor device as claimed in claim 3 , wherein the gate insulating film is formed on both side surfaces of the fin-shaped part.

10. The method of manufacturing the semiconductor device as claimed in claim 4 , wherein the gate insulating film is formed on both side surfaces of the fin-shaped part.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →