Apparatus for stacking integrated circuits
View Patent ↗A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack.
1. A chip stack assembly comprising:
a substrate that defines a plurality of surface mount pads;
a first chip having a first set of contacts extending outward;
a second chip having a second set of contacts extending outward therefrom;
at least one support member positioned on the substrate having a first surface with a first set of mounting pads positioned thereon and a second surface having a second set of mounting pads positioned thereon wherein the first and second surfaces are displaced from each other by a first distance in a first direction and wherein the first set of contacts are attached to the first set of mounting pads and the second set of contacts are attached to the second set of mounting pads such that the first and second chips are supported so as to be displaced from each other in the first direction, and wherein the at least one support member further includes at least one interconnect that interconnects at least one contact of the first and second set of contacts so as to electrically interconnect the at least one contact of first and second set of contacts;
a third chip having a third set of contacts extending outward therefrom;
a second support member positioned on the at least one support member, the second support member having a third surface with a third set of mounting pads positioned thereon and a fourth surface having a fourth set of mounting pads positioned thereon wherein the third and fourth surfaces are displaced from each other by the first distance in the first direction and wherein the first set of contacts are attached to the third set of mounting pads and the third set of contacts are attached to the fourth set of mounting pads such that the first and third chips are supported so as to be displaced from each other in the first direction, wherein the at least one support member further includes at least one via connection that extends in the first direction through the at least one support member to the substrate so that at least one individual contact of the first set of contacts can be electrically coupled to the surface mount pad of the substrate while being electrically isolated from the second set of contacts, and wherein the second support member further includes at least one interconnect that interconnects at least one contact of the first and third set of contacts so as to electrically interconnect the at least one contact of first, second, and third set of contacts, and wherein the at least one support member further includes a second via connection that extends in the first direction through the at least one support member to the substrate and wherein the second support member further includes at least one via connection that extends in the first direction through the second support member, to the second via of the at least one support structure to the substrate so that at least one individual contact of the third set of contacts can be electrically coupled to the surface mount pad of the substrate while being electrically isolated from the first and second set of contacts.
2. The chip stack assembly of claim 1 , wherein the at least one via connection and the second via connection are displaced from each other by a second distance in a second direction and whereby the second direction is substantially perpendicular to the first direction.
3. The chip stack assembly of claim 1 , wherein the first and second surfaces of the at least one support member are substantially parallel to each other.
4. The chip stack assembly of claim 1 , wherein the at least one support member comprises a plurality of support members.
5. The chip stack assembly of claim 1 , wherein the at least one support member comprises a printed circuit board.
6. The chip stack assembly of claim 1 , wherein the at least one via connection comprises:
a conductive trace positioned on the first surface that is electrically coupled to the mounting pad that is coupled to the individual contact of the first set of contacts;
a conductive element extending through a via opening formed between the first and second surfaces of the at least one support member so as to be electrically connected to the conductive trace; and
a solder bump formed on the second surface of the at least one support member adjacent the via opening so as to be electrically connected to the conductive element, and wherein the solder bump is positioned so as to be electrically coupled to the surface mount pad of the substrate.
7. The chip stack assembly of claim 1 , wherein the at least one interconnect that interconnects at least one contact of the first and second set of contacts comprises a via interconnection that extends through the at least one support structure.
8. A chip stack for mounting on a substrate having a plurality of contact pads comprising at least a first and a second chip and a conducting interconnecting means for interconnecting the chips and maintaining the chips in a stacked configuration so that the chips are interconnected with at least one contact on the first and second chips being electrically interconnected and wherein the interconnecting means interconnects the at least one of the contacts of the first chip to a contact pad on the substrate in a manner that isolates the contact of the first chip from the contacts of the second chip,
wherein the interconnecting means comprises a support structure having a first and a second side wherein the first side is positioned proximate the substrate to permit electrical connection between the support structure and the substrate and wherein the second side is substantially parallel to the first side,
wherein the support structure includes a plurality of vias extending between the first and second side wherein at least one via extends between the first and second side to permit electrical connection of the at least one contact of the first chip to the contact pad on the substrate in a manner that isolates the contact of the first chip from the contacts of the second chip, and
wherein the at least one of the vias extends to permit electrical interconnection between the at least one contacts on the first and second chip.
9. The chip stack of claim 8 , wherein the first and second chips are memory chips.
10. The chip stack of claim 8 , wherein the first and second chips are functionally identical.
11. The chip stack of claim 8 , wherein the support structure comprises a plurality of support structures.
12. The chip stack of claim 8 , wherein the support structure comprises one or more printed circuit boards.
13. The chip stack of claim 8 , wherein the support structure provides a support surface so as to maintain the first and second chips in a stacked configuration and wherein the support surface defines a first and second surface with the contacts of the first chip being connected to the first surface and the contacts of the second chip being connected to the second surface.