Binary-weighted delta-sigma fractional-
View Patent ↗A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.
1. A phase lock loop comprising:
a phase frequency detector providing a phase detected signal in response to a reference frequency signal and a divided frequency signal;
a charge pump providing a charge pump signal in response to the phase detected signal and a quantization error signal;
a loop filter providing a filtered control signal in response to the charge pump signal;
a voltage controlled oscillator for providing an output frequency signal in response to the filtered control signal;
a fractional divider providing the divided frequency signal in response to the output frequency signal and a fraction selection signal;
a delta-sigma modulator providing the fraction selection signal and an error signal in response to a divide selection signal; and
a quantizer generating a quantizer output signal fed to an integrator generating a integrator output signal fed to a differentiator generating a differentiator output signal fed to a binary-weighted digital-to-analog converter generating the quantization error signal.
2. The phase lock loop of claim 1 wherein the quantization error signal is an error signal from amplitude or phase modulation that is applied as an opposed current pulse in the charge pump.
3. The phase lock loop of claim 1 wherein the delta-sigma modulator is an L-th order MASH delta-sigma modulator, the quantizer quantizes the error signal, and multiplies the quantized error signal by a factor z −1 (1−z −1 ) L−1 by means of the integrator and differentiator.
4. The phase lock loop of claim 1 , wherein the delta-sigma modulator is an L-th order delta-sigma modulator.
5. The phase lock loop of claim 4 , wherein the integrator has a transfer function of e 2 z −1 (1−z −1 ) −1 , wherein e 2 is the quantizer output signal.
6. The phase lock loop of claim 5 , wherein the differentiator has a transfer function of (1−z −1 ) L , wherein L is the order of the of the delta-sigma modulator.
7. The phase lock loop of claim 6 , wherein the charge pump provides pulse width modulation with a fixed amplitude.
8. The phase lock loop of claim 4 , wherein the differentiator has a transfer function of (1−z −1 ) L , wherein L is the order of the of the delta-sigma modulator.
9. The phase lock loop of claim 1 , wherein the binary weighted digital-to-analog converter provides amplitude modulation with a fixed pulse width.
10. A phase lock loop comprising:
a phase frequency detector providing a phase detected signal in response to a reference frequency signal and a divided frequency signal;
a charge pump providing a charge pump signal in response to the phase detected signal and a quantization error signal;
a loop filter providing a filtered control signal in response to the charge pump signal;
a voltage controlled oscillator for providing an output frequency signal in response to the filtered control signal;
a fractional divider providing the divided frequency signal in response to the output frequency signal and a fraction selection signal;
an L-th order delta-sigma modulator providing the fraction selection signal and an error signal in response to a divide selection signal; and
a quantizer generating a quantizer output signal;
an integrator receiving the quantizer output signal generating a integrator output signal, wherein the integrator has a transfer function of z −1 (1−z −1 ) −1 ;
a differentiator receiving the integrator output signal and generating a differentiator output signal, wherein the differentiator has a transfer function of (1−z −1 ) L , wherein L is the order of the of the delta-sigma modulator; and
a digital-to-analog converter receiving the differentiator output signal and generating the quantization error signal comprising amplitude modulation with a fixed pulse width.
11. The phase lock loop of claim 10 , wherein the quantization error signal is an error signal from amplitude or phase modulation that is applied as an opposed current pulse in the charge pump.
12. The phase lock loop of claim 10 , wherein the delta-sigma modulator is an L-th order MASH delta-sigma modulator, the quantizer quantizes the error signal, and multiplies the quantized error signal by a factor z −1 (1−z −1 ) L−1 by means of the integrator and differentiator.