Phase change memory device capable of reducing disturbance and method of manufacturing the same
View Patent ↗A phase change memory device includes a plurality of word lines, a plurality of bit lines disposed to be crossed with the plurality of word lines, switching devices disposed at intersections of the plurality of word lines and the plurality of bit lines, heating electrodes connected to the switching devices respectively, heat absorbing layers disposed between adjacent heating electrodes, and phase change layers formed on the heating electrodes and the heat absorbing layers and extended in the same direction of the bit line.
1. A phase change memory device, comprising:
a plurality of word lines;
a plurality of bit lines disposed to be crossed with the plurality of word lines;
switching devices disposed at intersections of the plurality of word lines and plurality of the bit lines, respectively;
heating electrodes connected to the switching devices, respectively;
heat absorbing layers disposed between adjacent heating electrodes; and
phase change layers formed on the heating electrodes and the heat absorbing layers, and extended in the same direction as the bit line.
2. The phase change memory device of claim 1 , wherein the heat absorbing layers are disposed between the adjacent memory cells connected to the same bit line.
3. The phase change memory device of claim 2 , wherein the heat absorbing layer is comprised of a conduction layer which is electrically floating.
4. The phase change memory device of claim 1 , wherein each of the heating electrodes includes:
a heating pad formed on each of the switching devices; and
a heating pillar extended from a portion of the heating pad.
5. The phase change memory device of claim 4 , wherein the heat absorbing layer is comprised of the same material as the heating pillar.
6. A phase change memory device, comprising:
a semiconductor substrate where active regions are defined;
a plurality of word lines formed on the active regions;
a plurality of diodes formed on portions of the plurality of word lines;
heating electrodes formed on the plurality of diodes, respectively;
an interlayer insulating layer insulating between the heating electrodes;
heat absorbing layers formed in the interlayer insulating layer between adjacent heating electrodes, respectively;
phase change layers formed on the interlayer insulating layer, the heating electrodes and the heat absorbing layers; and
a plurality of bit lines disposed on the phase change layers and formed to be crossed with the plurality of word lines.
7. The phase change memory device of claim 6 , wherein the heat absorbing layers are contacted with the phase change layer which is extended without disconnection, and are disposed between heating electrodes adjacent to each other.
8. The phase change memory device of claim 6 , wherein the heat absorbing layer is comprised of a conduction layer which is electrically floating.
9. The phase change memory device of claim 6 , wherein each of the heating electrodes comprises:
a heating pad electrically connected to an upper portion of each of the switching devices; and
a heating pillar extended from a portion of the heating pad.
10. The phase change memory device of claim 9 , wherein the heat absorbing layer is comprised of the same material as the heating pillar.