Semiconductor device

1. A semiconductor device, comprising:

a first conductive-type first well and a second conductive-type second well configured over a substrate to contact each other;

a second conductive-type anti-diffusion region formed in the first conductive-type first well and being in contact with the second conductive-type second well; and

a gate electrode configured to simultaneously cross the first conductive-type first well, the second conductive-type anti-diffusion region, and the second conductive-type second well.

2. The semiconductor device of claim 1 , wherein the second conductive-type anti-diffusion region is disposed in the first conductive-type first well to contact an interface where the first conductive-type first well contacts the second conductive-type second well.

3. The semiconductor device of claim 1 , wherein an impurity doping concentration of the second conductive-type anti-diffusion region is higher than impurity doping concentrations of the first conductive-type first well and the second conductive-type second well.

4. The semiconductor device of claim 1 , further comprising:

a device isolation layer configured over the substrate;

a second conductive-type source region configured over the first conductive-type first well at one end of one side of the gate electrode; and

a second conductive-type drain region configured over the second conductive-type second well and spaced apart from one end of another side of the gate electrode by a predetermined distance.

5. The semiconductor device of claim 4 , wherein the second conductive-type anti-diffusion region is fully depleted based on a voltage supplied to the second conductive-type drain region.

6. The semiconductor device of claim 4 , wherein the device isolation layer is disposed between the gate electrode and the second conductive-type drain region and partially overlaps a lower portion of the gate electrode.