IP Library Granted Patent US 8,232,597
Granted Patent B2
US 8,232,597 · App. 12/836,506 · Granted Jul 31, 2012

Semiconductor-on-insulator with back side connection

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Quick Facts
Patent No.
US 8,232,597
App. No.
12/836,506
Granted
Jul 31, 2012
Kind
B2
Abstract

Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.

Claims (73)

1. A semiconductor-on-insulator structure comprising:

an electrically conductive layer;

an insulator layer being located above said electrically conductive layer, and partially vertically coextensive with said electrically conductive layer in an excavated insulator region;

an active layer being located above said insulator layer, and comprising an active device with a body;

a body contact physically connecting said electrically conductive layer and said body, being located in a first portion of said excavated insulator region;

wherein said electrically conductive layer couples said body contact to a contact in said active layer, said contact being located in a second portion of said excavated insulator region, said second portion being detached from said first portion;

a circuit branch comprising said body contact and said contact; and

wherein said circuit branch connects a gate of said active device to said body of said active device.

2. The semiconductor-on-insulator structure of claim 1 , further comprising:

a variable impedance circuit branch comprising said body contact and said contact;

wherein said variable impedance circuit branch is configured to have a high impedance when said active device is in an on state, and said variable impedance circuit branch is configured to have a low impedance when said active device is not in said on state.

3. The semiconductor-on-insulator structure of claim 2 , said variable impedance circuit branch further comprising:

a gate region of said active device;

wherein said variable impedance circuit branch latches said body to said gate voltage when said active device is in an off state.

4. The semiconductor-on-insulator structure of claim 3 , wherein said body contact is a hot-carrier diode junction.

5. The semiconductor-on-insulator structure of claim 4 , further comprising a handle wafer above said active layer.

6. The semiconductor-on-insulator structure of claim 5 , further comprising:

a landing pad formed above said body contact;

wherein said landing pad is comprised of a wider region of said body.

7. A semiconductor-on-insulator structure comprising:

an electrically conductive layer;

an insulator layer being located above said electrically conductive layer, and partially vertically coextensive with said electrically conductive layer in an excavated insulator region;

an active layer being located above said insulator layer, and comprising an active device with a body;

a body contact physically connecting said electrically conductive layer and said body, being located in a first portion of said excavated insulator region;

wherein said electrically conductive layer couples said body contact to a contact in said active layer, said contact being located in a second portion of said excavated insulator region, said second portion being detached from said first portion;

wherein said body contact is ohmic;

wherein said contact is directly below a diode formed in said active layer; and

wherein said diode is reversed biased when said active device is in an on state.

8. The semiconductor-on-insulator structure of claim 7 , further comprising:

a circuit branch comprising said body contact and said contact;

wherein said circuit branch connects a source of said active device to said body of said active device.

9. The semiconductor-on-insulator structure of claim 7 , further comprising:

a variable impedance circuit branch comprising said body contact and said contact;

wherein said variable impedance circuit branch is configured to have a high impedance when said active device is in an on state, and said variable impedance circuit branch is configured to have a low impedance when said active device is not in said on state.

10. The semiconductor-on-insulator structure of claim 9 , said variable impedance circuit branch further comprising:

a gate region of said active device;

wherein said variable impedance circuit branch latches said body to said gate voltage when said active device is in an off state.

11. The semiconductor-on-insulator structure of claim 10 , wherein said body contact is a hot-carrier diode junction.

12. The semiconductor-on-insulator structure of claim 11 , further comprising a handle wafer above said active layer.

13. The semiconductor-on-insulator structure of claim 12 , further comprising:

a landing pad formed above said body contact;

wherein said landing pad is comprised of a wider region of said body.

14. A semiconductor-on-insulator structure comprising:

an electrically conductive layer;

an insulator layer being located above said electrically conductive layer, and partially vertically coextensive with said electrically conductive layer in an excavated insulator region;

an active layer being located above said insulator layer, and comprising an active device with a body;

a body contact physically connecting said electrically conductive layer and said body, being located in a first portion of said excavated insulator region;

wherein said electrically conductive layer couples said body contact to a contact in said active layer, said contact being located in a second portion of said excavated insulator region, said second portion being detached from said first portion; and

a landing pad formed above said body contact;

wherein said landing pad is comprised of a wider region of said body.

15. The semiconductor-on-insulator structure of claim 14 , further comprising:

a circuit branch comprising said body contact and said contact;

wherein said circuit branch connects a source of said active device to said body of said active device.

16. The semiconductor-on-insulator structure of claim 14 , further comprising:

a variable impedance circuit branch comprising said body contact and said contact;

wherein said variable impedance circuit branch is configured to have a high impedance when said active device is in an on state, and said variable impedance circuit branch is configured to have a low impedance when said active device is not in said on state.

17. The semiconductor-on-insulator structure of claim 16 , said variable impedance circuit branch further comprising:

a gate region of said active device;

wherein said variable impedance circuit branch latches said body to said gate voltage when said active device is in an off state.

18. The semiconductor-on-insulator structure of claim 17 , wherein said body contact is a hot-carrier diode junction.

19. The semiconductor-on-insulator structure of claim 18 , further comprising a handle wafer above said active layer.

20. A semiconductor-on-insulator structure comprising:

an electrically conductive layer;

an insulator layer being at least partially vertically coextensive with said electrically conductive layer in an excavated insulator region;

an active layer being located above said insulator layer, and comprising an active device with a body; and

a body contact physically connecting said electrically conductive layer and said body;

wherein said electrically conductive layer couples said body contact to a contact in said active layer;

a circuit branch comprising said body contact and said contact; and

wherein said circuit branch connects a gate of said active device to said body of said active device.

21. The semiconductor-on-insulator structure of claim 20 , wherein:

said body contact is ohmic;

said contact is directly below a diode formed in said active layer; and

said diode is reversed biased when said active device is in an on state.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2016
From: QUALCOMM SWITCH CORP.
To: QUALCOMM INCORPORATED
Reel/Frame 038794/0663 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUS PATENT NUMBER 9029901 TO THE CORRECT PATENT NO. 9029201 AS PREVIOUSLY RECORDED ON REEL 036812 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE TERMINATION AND RELEASE OF GRANT OF SECURITY INTEREST AGAINST ALL PATENTS SET FORTH HEREIN. Recorded Oct 20, 2015
From: HSBC BANK AUSTRALIA LIMITED ABN 48 006 434 162
To: SILANNA SEMICONDUCTOR U.S.A., INC. (FORMERLY KNOWN AS IO SEMICONDUCTOR)
Reel/Frame 036907/0785 →
CHANGE OF NAME Recorded Oct 16, 2015
From: SILANNA SEMICONDUCTOR U.S.A., INC.
To: QUALCOMM SWITCH CORP.
Reel/Frame 036877/0140 →
TERMINATION AND RELEASE OF GRANT OF SECURITY INTEREST (PATENTS) Recorded Oct 7, 2015
From: HSBC BANK AUSTRALIA LIMITED ABN 48 006 434 162
To: SILANNA SEMICONDUCTOR U.S.A., INC. (FORMERLY KNOWN AS IO SEMICONDUCTOR)
Reel/Frame 036812/0429 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 024694 FRAME 0315. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNEE NAME SHOULD BE "IO SEMICONDUCTOR INCORPORATED". Recorded Jul 20, 2015
From: STUBER, MICHAEL A.; MOLIN, STUART B.; NYGAARD, PAUL A.
To: IO SEMICONDUCTOR INCORPORATED
Reel/Frame 036138/0857 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033134 FRAME: 0338. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Jul 15, 2015
From: IO SEMICONDUCTOR INCORPORATED
To: SILANNA SEMICONDUCTOR U.S.A., INC.
Reel/Frame 036109/0237 →
CHANGE OF NAME Recorded Jun 11, 2014
From: IO SEMICONDUCTOR, INC.
To: SILANNA SEMICONDUCTOR U.S.A., INC.
Reel/Frame 033134/0338 →
SECURITY AGREEMENT Recorded Feb 4, 2013
From: IO SEMICONDUCTOR INCORPORATED
To: HSBC BANK AUSTRALIA LIMITED
Reel/Frame 029751/0726 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2010
From: STUBER, MICHAEL A.; MOLIN, STUART B.; NYGAARD, PAUL A.
To: IO SEMICONDUCTOR, INC.
Reel/Frame 024694/0315 →