Semiconductor-on-insulator with back side support layer
View Patent ↗Embodiments of the present invention provide for the provisioning of efficient support to semiconductor-on-insulator (SOI) structures. Embodiments of the present invention may additionally provide for SOI structures with improved heat dissipation performance while preserving the beneficial electrical device characteristics that accompany SOI architectures. In one embodiment, an integrated circuit is disclosed. The integrated circuit comprises a silicon-on-insulator die from a silicon-on-insulator wafer. The silicon on insulator die comprises an active layer, an insulator layer, a substrate, and a strengthening layer. The substrate consists of an excavated substrate region, and a support region, the support region is in contact with the insulator layer. The support region and the strengthening layer are configured to act in combination to provide a majority of a required stabilizing force to the silicon-on-insulator die when it is singulated from the silicon-on-insulator wafer.
1. An integrated circuit comprising:
a silicon-on-insulator die from a silicon-on-insulator wafer, said silicon-on-insulator die having an active layer, an insulator layer, and a substrate;
wherein said substrate includes an excavated substrate region and a support region, said support region being in contact with said insulator layer; and
a strengthening layer providing an isolated thermal dissipation channel that contacts a lowest layer of metal in said active layer;
wherein said strengthening layer comprises a material with high fracture strength or high flexural strength; and
wherein said support region and said excavated substrate region form a single frame around the silicon-on-insulator die.
2. The integrated circuit from claim 1 , wherein:
said active layer has an area; and
said excavated substrate region covers a majority of said area of said active layer on said silicon-on-insulator die.
3. The integrated circuit from claim 1 , wherein said strengthening layer is disposed in said excavated substrate region.
4. The integrated circuit from claim 3 , wherein
said active layer has an area; and
said excavated substrate region covers a majority of said area of said active layer on said silicon-on-insulator die.
5. The integrated circuit from claim 1 , wherein said strengthening layer has high thermal conductivity.
6. The integrated circuit from claim 5 , wherein said strengthening layer is congruent with said excavated substrate region.
7. The integrated circuit from claim 3 , wherein: said insulator layer comprises an excavated insulator region; and said strengthening layer is disposed in said excavated insulator region.
8. The integrated circuit from claim 7 , wherein said strengthening layer has high thermal conductivity and is electrically insulating.
9. The integrated circuit from claim 7 , wherein said excavated insulator region is laterally coextensive with said lowest layer of metal in said active layer.
10. The integrated circuit from claim 9 , wherein said strengthening layer is congruent with a combination of said excavated substrate region and said excavated insulator region.
11. A method of fabricating an integrated circuit, the method comprising the steps of:
forming a silicon-on-insulator die from a silicon-on-insulator wafer, said silicon-on-insulator die having an active layer, an insulator layer, and a substrate;
removing a portion of said substrate from said silicon-on-insulator die on said silicon-on-insulator wafer to form an excavated substrate region in said substrate and a support region in said substrate;
depositing a strengthening layer on said excavated substrate region; and
singulating said silicon-on-insulator die from said silicon-on-insulator wafer;
wherein said strengthening layer comprises a material with high fracture strength or high flexural strength; and
wherein said support region and said excavated substrate region form a single frame around the silicon-on-insulator die.
12. The method from claim 11 , further comprising the step of:
preparing a strengthening layer deposition wafer, said strengthening layer
deposition wafer comprising said strengthening layer and a strengthening wafer substrate; wherein said strengthening layer has high thermal conductivity and is congruent with said excavated substrate region.
13. The method from claim 11 , further comprising the step of removing a portion of an insulator layer from said silicon-on-insulator wafer to form an excavated insulator region.
14. The method from claim 13 , wherein said excavated insulator region is laterally coextensive with a lowest layer of metal in said active layer.
15. The method from claim 14 , further comprising the step of:
preparing a strengthening layer deposition wafer, said strengthening layer deposition wafer comprising said strengthening layer and a strengthening wafer substrate;
wherein said strengthening layer is congruent with a combination of said excavated substrate region and said excavated insulator region.
16. The method from claim 15 , said strengthening layer comprising:
a set of isolated thermal dissipation channels; wherein each of said isolated thermal dissipation channels contacts said lowest layer of metal in said active layer.
17. The method from claim 16 , further comprising the step of:
removing said strengthening wafer substrate; wherein said removing said strengthening wafer substrate comprises dissolving a temporary bond material.
18. The integrated circuit from claim 1 , wherein said strengthening layer comprises one of diamond, diamond-like carbon, silicon carbide, aluminum oxide, aluminum nitride, beryllium oxide, beryllium nitride, or carbon nanotubes.