Semiconductor circuit
View Patent ↗A semiconductor circuit includes a pad, a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to code signals, a comparison section configured to compare a reference voltage and the voltage of the pad and generate a comparison signal, and a code generation section configured to calibrate code values of the code signals in response to the comparison signal.
1. A semiconductor circuit comprising:
a pad for signal input/output;
a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to code signals;
a comparison section configured to compare a reference voltage and the voltage of the pad and generate a comparison signal;
a code generation section configured to calibrate code values of the code signals in response to the comparison signal;
a data output driver connected to the pad, and configured to apply a predetermined impedance to the pad according to second code signals; and
an impedance calibration block configured to calibrate the second code signals such that an output voltage of an driver modeled in a similar way as the data output driver corresponds to a predetermined reference voltage.
2. The semiconductor circuit according to claim 1 , further comprising:
a control section configured to generate control signals for electrically isolating the pad driver from the pad during a write operation interval.
3. The semiconductor circuit according to claim 1 , wherein the code generation section comprises a counter.
4. A semiconductor circuit comprising:
a pad for signal input/output;
a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to code signals;
a first comparison section configured to compare a first reference voltage and the voltage of the pad and generate a first comparison signal;
a second comparison section configured to compare a second reference voltage and the voltage of the pad and generate a second comparison signal;
a code generation section configured to calibrate code values of the code signals in response to the first comparison signal and fix code values of the code signals in response to the first comparison signal and the second comparison signal;
a data output driver connected to the pad, and configured to apply a predetermined impedance to the pad according to second code signals; and
an impedance calibration block configured to calibrate the second code signals such that an output voltage of an driver modeled in a similar way as the data output driver corresponds to a predetermined reference voltage.
5. The semiconductor circuit according to claim 4 , further comprising:
a control section configured to generate control signals for electrically isolating the pad driver from the pad during a write operation interval.
6. The semiconductor circuit according to claim 4 , wherein the code generation section is configured to fix the code values of the code signals in response to the first comparison signal and the second comparison signal which are generated when the voltage of the pad has a level between the first reference voltage and the second reference voltage.
7. The semiconductor circuit according to claim 4 , wherein the code generation section comprises a counter.
8. A semiconductor circuit comprising:
a pad for signal input/output;
a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to control voltages;
a comparison section configured to compare a reference voltage and the voltage of the pad and generate a comparison signal;
a voltage generation section configured to calibrate levels of the control voltages in response to the comparison signal;
a data output driver connected to the pad, and configured to apply a predetermined impedance to the pad according to code signals; and
an impedance calibration block configured to calibrate the code signals such that an output voltage of an driver modeled in a similar way as the data output driver corresponds to a predetermined reference voltage.
9. The semiconductor circuit according to claim 8 , further comprising:
a control section configured to generate control signals for electrically isolating the pad driver from the pad during a write operation interval.
10. The semiconductor circuit according to claim 8 , wherein the voltage generation section comprises a charge pump.
11. A semiconductor circuit comprising:
a pad for signal input/output;
a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to control voltages;
a first comparison section configured to compare a first reference voltage and the voltage of the pad and generate a first comparison signal;
a second comparison section configured to compare a second reference voltage and the voltage of the pad and generate a second comparison signal;
a voltage generation section configured to calibrate levels of the control voltages in response to the first comparison signal and fix levels of the control voltages in response to the first comparison signal and the second comparison signal;
a data output driver connected to the pad, and configured to apply a predetermined impedance to the pad according to code signals; and
an impedance calibration block configured to calibrate the code signals such that an output voltage of an driver modeled in a similar way as the data output driver corresponds to a predetermined reference voltage.
12. The semiconductor circuit according to claim 11 , further comprising:
a control section configured to generate control signals for electrically isolating the pad driver from the pad during a write operation interval.
13. The semiconductor circuit according to claim 11 , wherein the voltage generation section is configured to fix the levels of the control voltages in response to the first comparison signal and the second comparison signal which are generated when the voltage of the pad has a level between the first reference voltage and the second reference voltage.
14. The semiconductor circuit according to claim 11 , wherein the voltage generation section comprises a charge pump.
15. A semiconductor circuit comprising:
data output drivers configured to apply a predetermined voltage to a pad according to first code signals;
an impedance compensation unit configured to compensate for a difference between a voltage of the pad and a reference voltage using second code signals; and
an impedance calibration block configured to calibrate the first code signals such that an output voltage of an driver modeled in a similar way as the data output drivers corresponds to a predetermined reference voltage.
16. The semiconductor circuit according to claim 15 , wherein the impedance compensation unit comprises:
a pad driver connected to the pad at an output terminal thereof and configured to calibrate the voltage of the pad in response to the second code signals;
a comparison section configured to compare the reference voltage and the voltage of the pad and generate a comparison signal; and
a code generation section configured to calibrate code values of the second code signals in response to the comparison signal.
17. The semiconductor circuit according to claim 16 , wherein the pad driver is configured to be electrically isolated from the pad in response to control signals.
18. The semiconductor circuit according to claim 17 , wherein the impedance compensation unit further comprises:
a control section configured to distinguish the write operation interval of the semiconductor circuit and generate the control signals.
19. The semiconductor circuit according to claim 15 , wherein the impedance compensation unit comprises:
a pad driver connected to the pad at an output terminal thereof and configured to calibrate the voltage of the pad in response to the second code signals;
a first comparison section configured to compare a first reference voltage and the voltage of the pad and generate a first comparison signal;
a second comparison section configured to compare a second reference voltage and the voltage of the pad and generate a second comparison signal; and
a code generation section configured to calibrate code values of the second code signals in response to the first comparison signal and fix code values of the second code signals in response to the first comparison signal and the second comparison signal.
20. The semiconductor circuit according to claim 19 , wherein the pad driver is configured to be electrically isolated from the pad in response to control signals.
21. The semiconductor circuit according to claim 20 , wherein the impedance compensation unit further comprises:
a control section configured to distinguish the write operation interval of the semiconductor circuit and generate the control signals.
22. The semiconductor circuit according to claim 19 , wherein the code generation section is configured to fix the code values of the second code signals in response to the first comparison signal and the second comparison signal which are generated when the voltage of the pad has a level between the first reference voltage and the second reference voltage.
23. A semiconductor circuit comprising:
a data output driver configured to apply a predetermined voltage to a pad according to preset code signals;
an impedance compensation unit configured to compensate for a difference between a voltage of the pad and a reference voltage using control voltages; and
an impedance calibration block configured to calibrate the preset code signals such that an output voltage of an driver modeled in a similar way as the data output driver corresponds to a predetermined reference voltage.
24. The semiconductor circuit according to claim 23 , wherein the impedance compensation unit comprises:
a pad driver connected to the pad at an output terminal thereof and configured to calibrate the voltage of the pad in response to the control voltages;
a comparison section configured to compare the reference voltage and the voltage of the pad and generate a comparison signal; and
a voltage generation section configured to calibrate levels of the control voltages in response to the comparison signal.
25. The semiconductor circuit according to claim 24 , wherein the pad driver is configured to be electrically isolated from the pad in response to control signals.
26. The semiconductor circuit according to claim 25 , wherein the impedance compensation unit further comprises:
a control section configured to distinguish the write operation interval of the semiconductor circuit and generate the control signals.
27. The semiconductor circuit according to claim 23 , wherein the impedance compensation unit comprises:
a pad driver connected to the pad at an output terminal thereof and configured to calibrate the voltage of the pad in response to the control voltages;
a first comparison section configured to compare a first reference voltage and the voltage of the pad and generate a first comparison signal;
a second comparison section configured to compare a second reference voltage and the voltage of the pad and generate a second comparison signal; and
a voltage generation section configured to calibrate levels of the control voltages in response to the first comparison signal and fix levels of the control voltages in response to the first comparison signal and the second comparison signal.
28. The semiconductor circuit according to claim 27 , wherein the pad driver is configured to be electrically isolated from the pad in response to control signals.
29. The semiconductor circuit according to claim 28 , wherein the impedance compensation unit further comprises:
a control section configured to distinguish the write operation interval of the semiconductor circuit and generate the control signals.
30. The semiconductor circuit according to claim 27 , wherein the voltage generation section is configured to fix the levels of the control voltages in response to the first comparison signal and the second comparison signal which are generated when the voltage of the pad has a level between the first reference voltage and the second reference voltage.
31. A semiconductor circuit comprising:
a pad for signal input/output;
one or more data output drivers connected to the pad at respective output terminals thereof and configured to apply a predetermined voltage to the pad during a data write operation interval of the semiconductor circuit;
an impedance compensation section connected to the pad and configured to compensate for a difference between a voltage of the pad and a reference voltage during the data write operation interval; and
an impedance calibration block configured to calibrate code signals such that an output voltage of an driver modeled in a similar way as the data output drivers corresponds to a predetermined reference voltage.
32. The semiconductor circuit according to claim 31 , wherein the impedance compensation section comprises:
a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to code signals and be electrically isolated from the pad in response to control signals;
a comparison section configured to compare a reference voltage and the voltage of the pad and generate a comparison signal;
a code generation section configured to calibrate code values of the code signals in response to the comparison signal; and
a control section configured to distinguish a data write operation interval and generate the control signals.
33. The semiconductor circuit according to claim 31 , wherein the impedance compensation section comprises:
a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to code signals and be electrically isolated from the pad in response to control signals;
a first comparison section configured to compare a first reference voltage and the voltage of the pad and generate a first comparison signal;
a second comparison section configured to compare a second reference voltage and the voltage of the pad and generate a second comparison signal;
a code generation section configured to calibrate code values of the code signals in response to the first comparison signal and fix code values of the code signals in response to the first comparison signal and the second comparison signal; and
a control section configured to distinguish a data write operation interval and generate the control signals.
34. The semiconductor circuit according to claim 31 , wherein the impedance compensation section comprises:
a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to control voltages and be electrically isolated from the pad in response to control signals;
a comparison section configured to compare a reference voltage and the voltage of the pad and generate a comparison signal;
a voltage generation section configured to calibrate levels of the control voltages in response to the comparison signal; and
a control section configured to distinguish a data write operation interval and generate the control signals.
35. The semiconductor circuit according to claim 1 , wherein the impedance compensation section comprises:
a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to control voltages and be electrically isolated from the pad in response to control signals;
a first comparison section configured to compare a first reference voltage and the voltage of the pad and generate a first comparison signal;
a second comparison section configured to compare a second reference voltage and the voltage of the pad and generate a second comparison signal;
a voltage generation section configured to calibrate levels of the control voltages in response to the comparison signal and fix levels of the control voltages in response to the first comparison signal and the second comparison signal; and
a control section configured to distinguish a data write operation interval and generate the control signals.